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Formation method of semiconductor structure

A technology of semiconductor and isolation structure, applied in the field of semiconductor structure formation, can solve the problems of affecting transistor performance, uneven doping concentration of fin sidewalls, etc., and achieve the effects of increasing uniformity and reducing blocking effect.

Active Publication Date: 2020-11-03
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the formation method of the semiconductor structure easily makes the doping concentration of the sidewall of the fin portion uneven, which affects the performance of the transistor.

Method used

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  • Formation method of semiconductor structure

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Embodiment Construction

[0029] There are many problems in the formation method of the semiconductor structure, for example: the formation method of the semiconductor structure tends to make the doping concentration of the sidewall of the fin portion uneven, which affects the performance of the transistor.

[0030] In combination with a method for forming a semiconductor structure, the reason why the method for forming the semiconductor structure is easy to reduce the thickness of the isolation layer in the semiconductor structure is analyzed:

[0031] figure 1 and figure 2 It is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0032] Please refer to figure 1 , providing a base, the base includes an NMOS region A and a first PMOS region B and a second PMOS region C respectively located on both sides of the NMOS region A; the base includes: a substrate 100; Fins; isolation structures 102 on the substrate 100 between said initial fins. The portion of ...

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Abstract

The invention provides a method for forming a semiconductor structure. The method includes the steps of providing a substrate including a first region and a second region adjacent to each other, wherein the substrate comprises a substrate and a first fin portion including a first side facing the second region and a second side; forming a pattern layer on the second region, the pattern layer covering the second region or exposing a portion of the second region adjacent to the first region; performing ion implantation on one sidewall of the first fin by using the pattern layer as a mask, implanting doping ions into the bottom of the first fin; performing ion implantation into the first sidewall when the pattern layer exposes a portion of the second region adjacent to the first region; performing ion implantation into the second sidewall when the pattern layer covers the second region; and performing a diffusion process to diffuse doping ions in the first fin, wherein the ion implantationis performed on the side of the first fin, so that it is easy to prevent the doping ions from being implanted into the bottom of the fin due to photoresist blocking, thereby reducing the non-uniformity of the doping concentration on the sidewall of the first fin.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous progress of semiconductor technology, semiconductor devices are developing towards high integration and high quality, and the feature size of semiconductor devices is reduced accordingly. [0003] The reduction of the feature size of the semiconductor device, especially the reduction of the width of the gate structure, makes the length of the channel under the gate structure correspondingly reduced. The reduction of channel length in transistors increases the possibility of charge punching between source and drain, and easily causes channel leakage current. In order to reduce channel leakage current, semiconductor technology introduces fin field effect transistors. [0004] In the FinFET, the gate structure is on the fin, so the channel can be formed on the top ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP