Embedded substrate

Abstract

The invention relates to the technical field of integrated circuits, and discloses an embedded substrate. The embedded substrate is used for solving a problem that an embedded substrate limits the further improvement of the packaging integration degree in the prior art because all chips of the embedded substrate occupies a bigger space and the reliability of products is lower. The embedded substrate comprises a substrate, wherein two sides of the substrate in the thickness direction are respectively provided with at least one first cavity and at least two first electronic devices, and each first electronic device is corresponding to one first cavity; packaging layers which are respectively disposed in each first cavity and respectively wrap the first electronic devices in the first cavities, and is provided with a plurality of first connection holes, wherein each first connection hole is corresponding to one pin of one first electronic device, and is connected with a corresponding pin;and a conductive circuit layer, wherein a part of the conductive circuit layer is disposed in the first connection holes to be connected with the pins corresponding to the first connection holes.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to an embedded substrate. Background technique [0002] As the design trend of electronic products is moving toward miniaturization and thinning, the packaging integration of product modules is also increasing. At present, high-density interconnection integration technology that embeds chips in substrates has emerged in the industry. The structure of the embedded substrate made by this technology is as follows figure 1 as shown, figure 1 It is a schematic cross-sectional structure diagram of a common embedded substrate at present, which includes a substrate 10 and a first chip 20 and a second chip 30 packaged in the substrate 10, wherein a plurality of cavities 11 are formed on the substrate 10 , each cavity 11 is packaged with a first chip 20 or a second chip 30 by resin 40, the pads 21 of the first chip 20, the front pads 31 and the back pads 32 of the seco...

AI Technical Summary

Problems solved by technology

[0004] This application provides an embedded substrate to solve the problem that the embedded substrate in the prior art has a large area occupied by all chips and low product reliability, which limits the further improvement of the package integration of the embedded substrate

Images