A Noc Test Planning Method Based on Sine-Cosine Algorithm

Abstract

The invention discloses a network-on-chip (NoC) test planning method based on a sine-cosine algorithm. A special TAM parallel test method is used for building a test planning model to test a NoC underthe condition of meeting power consumption and pin constraints. Sine and cosine fluctuation is performed around an optimal solution via a swarm, and optimization is performed on a plurality of randomoperators and an adaptive variable to achieve the purpose of minimizing test time. A contrast experiment is performed on an ITC'02test benchmarks, and a result indicates that compared with a particleswarm optimization (PSO) algorithm, the provided algorithm can acquire shorter test time.

Description

technical field [0001] The invention relates to the technical field of Network-on-Chip (NoC), in particular to a NoC test planning method based on a sine-cosine algorithm. Background technique [0002] In order to solve the problem of quick time to market, chip manufacturers have adopted the method of integrating a large number of transistors and reusing IP (Intellectual Property) cores on a single chip. However, when SoC (System-on-Chip) becomes denser and denser, the traditional bus-based SoC is subject to many limitations, such as global clock synchronization, communication bandwidth, scalability and performance. In order to eliminate the limitation brought by the bus structure, NoC design specification came into being. A typical NoC system based on packet switching interconnection structure includes IP core, router, resource interface and interconnection line. However, testing NoC systems presents new challenges compared to conventional SoCs. [0003] Like the traditi...

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However, testing NoC systems presents new challenges compared to conventional SoCs

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