Lithographic patterning to form fine pitch features

Abstract

Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening andsecond openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resistmaterial that is removable selective to the hardmask layer.

Description

technical field [0001] The present invention relates to the manufacture of integrated circuits and semiconductor devices, and more particularly to methods for forming photolithographic patterns of interconnect structures of a chip. Background technique [0002] A back-end-of-line (BEOL) interconnect structure may be used to electrically couple device structures fabricated on a substrate during a front-end-of-line (FEOL) process. The back-end-of-line interconnect structure may be formed using a dual-damascene process, in which vias and trenches etched into a dielectric layer are simultaneously filled with metal to create a metallization level. In a via-first, trench-last dual damascene process, a via is formed in a dielectric layer, and then a trench is formed in the dielectric layer above the via , the via is not filled during the etch process that forms the trench. In a single damascene process, the vias and trenches are formed in different dielectric layers and filled wi...

AI Technical Summary

Problems solved by technology

As the technology nodes of advanced semiconductor devices shrink to 7nm and below, the ability to form features in a low-k dielectric material with multi-patterning technology becomes more and more challenging

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