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A power chip packaging method and structure

A technology of power chip and packaging method, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve problems such as assembly errors of IGBT devices, meet the requirements of ensuring error accuracy, simplify assembly processes, and improve heat dissipation capacity Effect

Active Publication Date: 2020-08-25
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is that the packaging method of IGBT devices in the prior art is easy to introduce artificial assembly errors

Method used

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  • A power chip packaging method and structure
  • A power chip packaging method and structure
  • A power chip packaging method and structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] This embodiment provides a power chip packaging method, which is suitable for packaging power chips (such as IGBT chips), such as figure 1 As shown, the method includes the following steps:

[0037] S11: Connect the first metal pad 50, the power chip 30 and the second metal pad 10 to form a connection sub-module; Figure 2A and 2BAs shown, that is, before the plastic packaging, the first metal pad 50, the power chip 30 and the second metal pad 10 are first connected to form a connection sub-module (the connection sequence can be adjusted according to actual needs), so that after the plastic packaging In this case, it is only necessary to assemble and connect the sub-module as a whole, because the relative positions of the components of the connected sub-module have been fixed, thus avoiding the error caused by the assembly of a single part during the assembly process, and simplifying the assembly process .

[0038] S12: Plastic sealing the formed connection sub-modul...

Embodiment 2

[0056] This embodiment provides a power chip packaging structure, such as image 3 As shown, it includes: a first cover plate 3, and a boss is arranged on the first cover plate 3; a power chip sub-module 1, including a plastic package case 70 and a connection sub-module set in the plastic package case 70, wherein the connection sub-module The set includes a first metal pad 50, a power chip 30 and a second metal pad 10 sintered together, and a first sintered layer 40 is arranged between the first metal pad 50 and the power chip 30, and the power chip 30 The second sintering layer 20 is arranged between the second metal gasket 10, which are respectively used to sinter the three together in a vacuum sintering furnace through auxiliary tools with controllable temperature, pressure and thickness. The power chip sub-module 1 is set On the boss of the first cover 3 ; the second cover 2 , the second cover 2 is arranged on the power chip sub-module 1 . Compared with the prior art, the...

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Abstract

The invention provides a power chip packaging method and structure. The method comprises steps that a first metal pad, a power chip and a second metal pad are connected to form a connection sub modulethrough the sintering process; plastic packaging of the formed connection sub module is carried out. According to the method, the first metal pad, the power chip and the second metal pad are firstlyconnected to form the connection sub module, plastic packaging of the formed connection sub module is carried out, assembling single parts is not required in the assembling process, assembling operation is simplified, artificial assembling errors are reduced, connection is carried out through the sintering process, thermal resistance is reduced, heat radiation performance of devices is improved, the plastic packaging process is employed for packaging, gaps are completely filled through plastic packaging materials, and a hidden trouble of sparking discharging is eliminated. The plastic packaging structure is employed to substantially improve uniformity of the sub module assembly process, error precision requirements of large-scale ship parallel connection is effectively guaranteed, and device reliability is improved.

Description

technical field [0001] The invention relates to the field of packaging technology, in particular to a power chip packaging method and structure. Background technique [0002] Press-pack packaging is the latest packaging form of high-power IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) devices. Compared with traditional soldered IGBT (Soldered IGBT Module), press-pack IGBT (Press-pack IGBT) The thermodynamic and electrical connection is realized by using pressure, and double-sided heat dissipation is ensured. The crimp-type IGBT is considered to be an ideal device for high-power applications and applications with large fluctuations in output power, and can meet the requirements of high-voltage direct current transmission and new energy grid-connected switching devices. In addition, the reliability of the crimp-type IGBT is very high, and it can also meet the requirements of the power system for high reliability of power supply. [0003] At prese...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L23/367H01L23/31
CPCH01L21/50H01L21/56H01L23/3107H01L23/367
Inventor 武伟张朋韩荣刚林仲康石浩田丽纷张喆李现兵
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD