A low on-resistance flatness analog switch with leakage current cancellation technology

Abstract

The invention relates to a low on-resistance flatness analog switch with leakage current elimination technology, which belongs to the technical field of semiconductors. It includes: a first PMOS transistor and a first NMOS transistor; the source and drain of the first PMOS transistor are respectively connected to the source and drain of the first NMOS transistor, and serve as the input and output ends of the analog switch, the first The gate of the PMOS transistor and the first NMOS transistor is connected to the control signal; it also includes a substrate control transistor, a gate control circuit I and a gate control circuit II, and the gate control circuit I can be composed of a third PMOS transistor and a third NMOS transistor. The gate control circuit II may be composed of a fourth PMOS transistor and a fourth NMOS transistor. In the present invention, the gate terminal control circuit is added on the basis of the flatness design of the on-resistance of the traditional analog switch, so that the flatness of the on-resistance of the analog switch is optimized to a certain extent, and at the same time, the transient leakage current generated at the output port at the moment of switching of the analog switch is also reduced. be eliminated.

Description

technical field [0001] The invention belongs to the technical field of semiconductors and relates to a low on-resistance flatness analog switch with leakage current elimination technology. Background technique [0002] In the prior art, CMOS [Complementary Metal Oxide Semiconductor; Complementary Metal Oxide Semiconductor] such as figure 1 As shown, the analog switch is composed of two parts, a P-channel MOS field effect transistor P1 and an N-channel MOS field effect transistor N1. Normally, the potentials of the gates 2 and 3 of the P1 and N1 transistors are inverse signals, and the level of the gates 2 and 3 determines whether the switch is turned on or off. [0003] The structure adopts a single-well process, that is, the substrate 5 of the NMOS transistor is Psub, which is always connected to the lowest potential VSS; the substrate 4 of the PMOS transistor is an N-well, which is floating, and there are usually two connection methods, which are connected to the highest ...

AI Technical Summary

Problems solved by technology

If the transistor substrate 4 is connected to the source terminal 6, such as image 3 , when the switch is turned off, due to the uncertainty of the voltages of terminals 1 and 6, the voltage of terminal 1 may be higher than that of terminal 6, so that the diodes from terminal 1 to terminal 6 form a path, and the switch cannot be turned off; if the transistor substrate 4 is connected to VDD ,like figure 2 , then when the voltages of terminals 1 and 6 change from VSS to VDD, the threshold voltage Vth of the PMOS transistor will increase due to the substrate bias effect, and the on-resistance flatness will deteriorate

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