Method for building functional verification platforms of designs based on LOCAL BUS bus

Abstract

The invention discloses a method for building functional verification platforms of designs based on a LOCAL BUS bus. The method, for the internal register and ram module information document, chip initialization control document, and arbitration module working method description document of the currently tested designs, uses a variety of automation scripts to complete the generation, operation, and control of verification test vectors, then runs the test vectors, and generates a test report to complete the test process. The method automatically completes the setup and operation of the verification platforms by the use of the automation scripts, achieves universal read-write test for each design based on the LOCAL BUS according to the standard LOCAL BUS protocol design verification platformtest command, and achieves correct test for a specific memory module by use of the internal register and ram module information document. The method is easy in implementation, simple in process, efficient and stable, greatly shortens the development cycles of building functional verification platforms for different designs based on the LOCAL BUS, and improves the efficiency of functional verification.

Description

technical field [0001] The invention relates to the field of IC design verification, in particular to a method for building a function verification platform for design based on the LOCAL BUS bus. Background technique [0002] At present, the rapid progress of integrated circuit manufacturing technology and the increasing market demand for highly integrated products have led to an exponential increase in the complexity of integrated circuits. As the complexity of integrated circuits increases, the difficulty of verification increases at a higher rate. Therefore, improving the realization ability of the verification work has become the focus and difficulty of the development of large-scale integrated circuits. [0003] Core connect is a bus specification for core+ASIC development or SoC design proposed by IBM, which can provide an efficient and complete connection method for the entire system. It includes three different bus types, namely the processor internal bus LOCAL BUS...

AI Technical Summary

Problems solved by technology

Therefore, the LOCAL BUS bus is the most important and complex part of the Core connect bus. It is very cumbersome and complicated to develop a verification platform for each design based on the LOCAL BUS bus to simulate and test the internal registers and ram modules of the design.