Method and device for monitoring axi bus

Abstract

A method for monitoring an AXI bus, applied in a device (010) for monitoring an AXI bus. In the device (010) for monitoring the AXI bus, a monitoring master module (101) is in serial connection to a monitoring slave module (102) by means of a serial protocol interface line to form a closed loop consisting of the monitoring master module (101) and the monitoring slave module (102). The method comprises: the monitoring master module receives a serial protocol command sent by a chip to be detected (201); convert the serial protocol command into a customized serial bit frame command (202); send the customized serial bit frame command to the monitoring slave module (203); the monitoring slave module converts the customized serial bit frame command into a universal parallel data read / write interface command (204); monitor, according to the universal parallel data read / write interface command, the AXI bus of the chip to be detected to obtain status information of the AXI bus (205); send the status information of the AXI bus to the monitoring master module (206); the monitoring master module determines, according to the status information of the AXI bus, the status of the AXI bus of the chip to be detected (207). Also provided are a device (010) for monitoring an AXI bus, and a computer readable storage medium.

Description

technical field [0001] The present invention relates to an Advanced Extensible Interface (AXI) bus technology of a System on a Chip (SoC), in particular to a method and device for monitoring the AXI bus. Background technique [0002] Once the chip is produced, it is a black box from the outside, with very limited means of observation and debugging, unlike software, which can be debugged by modifying the program at any time, or step by step by setting some breakpoints; and for FPGA, It is also possible to capture some useful waveforms in real time through the waveform capture software to observe the internal working status of the FPGA, and the waveforms that need to be captured are also realized through programming; currently chips often use SoC systems, using AXI bus for data transmission , AXI bus is a high-performance, high-bandwidth and low-latency on-chip bus. [0003] figure 1 It is a schematic diagram of the structure of AXI bus interconnection in a typical SoC syste...

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Problems solved by technology

[0003] figure 1 It is a schematic diagram of the structure of AXI bus interconnection in a typical SoC system, such as figure 1 In the typical SoC system shown, there are 3 masters (master modules) and 4 slaves (slave modules) hanging on the AXI bus; for example, the following scenario will appear in the application: master0 initiates a write access to slave2, and then master2 Read the data previously updated to slave2, but after master2 reads the data back, it is found that it is not the expected data; because in the SoC system using the AXI bus, the fault may be that the AXI bus itself hangs up, the response error or other reasons , so in the process of locating the problem, try to protect the site; however, there is currently no effective method for monitoring the AXI bus. For SoC chips with huge functions, once a problem occurs, it is very difficult to locate the problem

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