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Non-volatile memory apparatus

A non-volatile, memory technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems of increasing the manufacturing cost of memory devices, circuit complexity and reducing product yield, so as to improve production yield and reduce circuit effect of complexity

Active Publication Date: 2018-06-01
IOTMEMORY TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The higher the complexity of the circuit will greatly reduce the product yield, and increase the manufacturing cost of the memory device

Method used

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Embodiment Construction

[0085] figure 1 For a schematic diagram of a non-volatile memory device shown according to an embodiment of the present invention, please refer to figure 1 . The non-volatile memory device includes a memory cell array 102, a column decoder 104, a high-voltage decoder 106, a row decoder 108, and a sense amplifier 110. The memory cell array 102 is coupled to the column decoder 104 and the high-voltage decoder. 106 and the row decoder 108 , the sense amplifier 110 is coupled to the row decoder 108 . Further, the memory cell array 102 includes a plurality of memory cells, and each memory cell may be coupled to the column decoder 104 through the word line, and coupled to the row decoder 108 and the sense amplifier 110 through the bit line.

[0086] The detailed structure of the memory cell can be as follows Figure 2A shown in Figure 2A In an embodiment, the memory cell MC may include a stack structure 220, an auxiliary gate dielectric layer 230, an erase gate dielectric layer...

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Abstract

The invention provides a non-volatile memory apparatus. The non-volatile memory apparatus is provided with a memory cell array, a column decoder and a high-voltage decoder. The high-voltage decoder comprises multiple transmission channel circuits and multiple first pull-down circuits. When memory cells corresponding to all the transmission channel circuits are erased, current is limited to transmit to corresponding erasing gate electrodes according to a gate electrode-erasing control signal. When the first pull-down circuits are erased by selected memory cells, erasing gate electrodes of non-selected memory cells are connected to the ground. Circuit complexity of the non-volatile memory apparatus is effectively reduced and production yield of the non-volatile memory apparatus is increased.

Description

technical field [0001] The present invention relates to a memory device, and in particular to a non-volatile memory device. Background technique [0002] Non-volatile memory has been widely used in personal computers and electronic devices due to its advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure. [0003] With the advancement of memory-related technologies, the capacity of memory devices is increasing, the size is becoming smaller and smaller, and the circuit complexity is increasing day by day. The higher the complexity of the circuit, the lower the yield rate of the product will be greatly reduced, and the manufacturing cost of the memory device will be increased. Contents of the invention [0004] The invention provides a non-volatile memory device, which can effectively reduce the circuit complexity of the non-volatile memory device and improve the production yield of the non-volatile me...

Claims

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Application Information

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IPC IPC(8): G11C7/10
CPCG11C7/1063G11C7/109
Inventor 黄义欣
Owner IOTMEMORY TECH
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