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Semiconductor device and semiconductor integrated system

An integrated system and semiconductor technology, applied in semiconductor devices, electric solid state devices, digital memory information, etc., can solve the problems of testing and debugging memory chips without direct access to memory chips.

Pending Publication Date: 2018-06-05
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, this embodiment is a method for a logic chip to access a memory chip, and this embodiment does not disclose a method for directly accessing a memory chip and testing and debugging a memory chip

Method used

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  • Semiconductor device and semiconductor integrated system
  • Semiconductor device and semiconductor integrated system
  • Semiconductor device and semiconductor integrated system

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0023] figure 1 is a diagram for explaining the configuration of the semiconductor device 1 according to the first embodiment.

[0024] Such as figure 1 As shown, the semiconductor device 1 is a semiconductor device in which a plurality of chips are mounted in a common package.

[0025] Specifically, the semiconductor device 1 includes a logic chip PU and a memory chip MD.

[0026] The logic chip PU is a chip such as a processor unit combined so as to realize a predetermined function.

[0027] The memory chip MD is a chip including memory elements that store data.

[0028] The logic chip PU is coupled with the memory chip MD, and transmits and receives clocks, control signals, addresses, and data to and from the memory chip MD. For example, the memory chip MD operates in synchronization with the clock from the logic chip PU. The memory chip MD is accessed according to the input of the control signal and the address from the logic chip PU. For example, data is read from t...

no. 2 example

[0078] Figure 8 is a diagram for explaining the structure of the semiconductor device 1# of the second embodiment.

[0079] Such as Figure 8 As shown, semiconductor device 1# mounts a plurality of memory chips MDA and MDB and a common logic chip PU in a common package.

[0080] Each of the memory chips MDA and MDB is configured to be accessible from the logic chip PU.

[0081] other parts and figure 1 The components are the same, so their detailed description will not be repeated.

[0082] The memory chip MDA includes a test circuit TCA and a serial bus interface circuit SIFA.

[0083] The memory chip MDB includes a test circuit TCB and a serial bus interface circuit SIFB.

[0084] Test circuits TCA and TCB are basically the same as test circuit TC.

[0085] The serial bus interface circuits SIFA and SIFB are basically the same as the serial bus interface circuit SIF.

[0086] An external terminal SDAP and an external terminal SCLP are provided as common terminals of ...

no. 3 example

[0094] Figure 9 is a diagram for explaining the configuration of the system board SD# based on the third embodiment.

[0095] Such as Figure 9 As shown, on a system board SD# (motherboard), an overall control unit MCU that controls the entire system board SD#, a plurality of semiconductor devices 1A to 1C, and a serial bus SB are mounted.

[0096] The semiconductor device 1A mounts a plurality of memory chips MDA, MDB, MDC, and MDD and a logic chip PU in a common package.

[0097] Each of the memory chips MDA, MDB, MDC, and MDD is configured to be accessible from the logic chip PU. other parts and figure 1 The components are the same, so their detailed description will not be repeated.

[0098] In this example, a case where identification information is assigned to each of the memory chips MDA to MDD is shown. Furthermore, a case is shown in which identification information is also assigned to each of the plurality of semiconductor devices 1A to 1C.

[0099] Specifical...

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Abstract

The present disclosure relates to a semiconductor device and a semiconductor integrated system. A semiconductor device that can access and test a memory chip in a simple manner is provided. The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2016-232846 filed on Nov. 30, 2016 including specification, drawings and abstract is incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates to a semiconductor device and a semiconductor integrated system, and to a semiconductor device including a memory chip. Background technique [0004] In which a large-capacity memory chip and a logic chip with a specific function (such as image processing) are installed in the same package, it is called MCP (Multi Chip Package, multi-chip package) or MCM (Multi-Chip Module, multi-chip module) Semiconductor devices are becoming commonplace. [0005] In this regard, Japanese Unexamined Patent Application Publication No. 2003-77296 proposes in which a self-test circuit (BIST: Built-In Self-Test Circuit) is mounted on a logic chip in an MCP and performed on a memory chip packaged in th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12G11C29/48G11C29/56
CPCG11C29/1201G11C29/48G11C29/56G11C2029/0401H01L24/13H01L24/17H01L25/0652H01L2224/13025H01L2224/16227H01L2224/17181H01L2924/1434H01L2924/15192H01L2924/15311G11C29/26G11C29/32G06F13/1673H01L24/16H01L25/18H01L2224/16146H01L2924/1431H01L2924/1436G11C11/4076G11C11/408G11C11/4093G11C29/18H01L25/0657H01L2224/16225H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06565H01L2225/06586H01L2225/06596
Inventor 佐藤创
Owner RENESAS ELECTRONICS CORP