Test and verification system for reconfigurable fpga and dsp tightly coupled architecture

Abstract

The invention discloses a testing and verifying system for an FPGA and DSP tight coupling framework capable of being reconstructed and configured. The testing and verifying system for the FPGA and DSPtight coupling framework capable of being reconstructed and configured comprises a visual sub-system, a feedback control sub-system and a target machine sub-system which is in data connection with the feedback control sub-system, wherein the visual sub-system communicates with the feedback control sub-system through a network, receives and analyzes feedback signals of the feedback control sub-system, and transmits network signals to the feedback control sub-system, the network signals comprises control signals and testing signals; the feedback control sub-system is in charge of communicationbetween the target machine sub-system and external data, and is used for implementing transferring and dispatching of all data in the FPGA and DSP tight coupling framework capable of being reconstructed and configured; and the target machine sub-system is used for rapidly constructing a target prototype which is capable of being reconstructed and configured and comprises an FPGA and DSP chip framework. By the testing and verifying system, normal function testing and abnormal fault testing on tested product software can be realized, and functions of signal monitoring and tampering and fault injection between FPGA and DSP can be fulfilled.

Description

technical field [0001] The invention belongs to the technical field of embedded DSP and FPGA software testing, and in particular relates to a test verification system under the tight coupling framework of FPGA and DSP. Background technique [0002] In order to improve the real-time performance of system processing, many equipment products use parallel processing devices such as DSP and FPGA. However, due to the timing correlation and the distribution of processing logic, it is difficult to reproduce the faults and capture the signals of the FPGA and DSP tightly coupled architecture system in the existing technology, and only the pins of the FPGA and the peripheral environment or the DSP and the peripheral environment can be observed signal, and the signal between the two is difficult to observe. At the same time, in the current test environment, due to the differences in peripheral environments such as interfaces between equipment products with the same architecture, test e...

AI Technical Summary

Problems solved by technology

However, due to the timing correlation and the distribution of processing logic, it is difficult to reproduce the faults and capture the signals of the FPGA and DSP tightly coupled architecture system in the existing technology, and only the pins of the FPGA and the peripheral environment or the DSP and the peripheral environment can be observed signal, and the signal between the two is difficult to observe

At the same time, in the current test environment, due to the differences in the peripheral environment such as interfaces of equipment products with the same architecture, the test equipment must be customized and dedicated to special use, resulting in a great waste of resources.

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