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Chip packaging structure and method

A chip packaging structure, chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of unstable adhesive thickness, unstable process, low efficiency, etc., to improve mechanical strength and reliability, shorten Process time, effect of reducing process steps

Active Publication Date: 2018-06-29
MICROARRAY MICROELECTRONICS CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 1. The process speed is slow and the efficiency is low, and the steps include surface cleaning, gluing, covering, baking and other steps;
[0005] 2. The process is unstable and the yield rate is low; if the thickness of the adhesive is unstable, the surface of the final product will be uneven; if the thermal expansion coefficient of the packaging material is greater than that of the substrate and greater than that of the chip, the chip is highly unstable and the packaging surface Concave warping occurs, and it needs to be ground before being attached to the hard cover

Method used

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  • Chip packaging structure and method
  • Chip packaging structure and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0093] Please refer to figure 1 What is shown is a schematic cross-sectional view of the state after the chip packaging structure is packaged. The bottom of the chip is the substrate 2 for mounting the chip. The chip is electrically connected to the substrate 2 and fixed. The corelayer (metal layer) under the soldermask (solder mask), and the soldermask (solder mask) under the metal layer, the soldermask (solder mask) is used to protect the corelayer (metal layer) in the middle, preventing the corelayer (metal layer) ) problems such as short circuits occur in the welding process, and the thickness of the multi-layer substrate is between 100 microns and 300 microns. The chip includes a functional surface 31 and a non-functional surface 32 opposite to the functional surface. The functional surface 31 contains circuits for performing target functions, including sensing components and driving circuits for sensing fingerprint characteristics. The functional surface 31 is arranged ...

Embodiment 2

[0142] refer to Figure 5a and Figure 5b Compared with Embodiment 1, the difference in technical solution is that in step S4

[0143] Before the hard cover, the filling material and the substrate on which the chip is fixed are put into the film lamination equipment, the filling material and the hard cover 6 are bonded in advance.

[0144] Follow the steps:

[0145] S41: paste the release film 15 in the first mold 11 of the compression molding equipment

[0146] S42: Put the hard cover plate 6 on the release film 15 in the first mold, with the first surface 61 facing upward;

[0147] S43: placing the packaging compound 51 on the first surface 61 of the hard cover 6;

[0148] S44: fixing the substrate 2 on which the chip 3 is fixed on the second mold 12;

[0149] S45: Clamp the second mold 12 and the first mold 11, vacuumize and heat, so that the encapsulation material 51 is cured to form the encapsulation layer 5;

[0150] S46: demoulding to obtain the package structure ...

Embodiment 3

[0153] refer to Figure 6a and Figure 6b The difference from Embodiment 1 or Embodiment 2 is that in step S4, the encapsulating material 51 is not pre-placed in the molding device 1 but is a fluid encapsulating material injected after vacuuming and heating, specifically including steps:

[0154] S41: Paste the release film 15 in the first mold of the compression molding equipment;

[0155] S42: Put the hard cover plate 6 on the release film in the first mold 11, with the first surface 61 facing upward;

[0156] S43: fixing the substrate 2 on which the chip 4 is fixed on the second mold 12;

[0157] S44: Clamp the second mold 12 and the first mold 11, vacuumize and heat, inject the fluid encapsulation compound 51, and solidify the encapsulation compound to form the encapsulation layer 5;

[0158] S45: demoulding to obtain a chip packaging structure.

[0159] The rest of the structures and packaging methods are the same as those in Embodiment 1, and will not be repeated her...

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PUM

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Abstract

The invention relates to a chip packaging structure and a corresponding packaging method. The packaging structure mainly comprises a substrate, a chip, a filling material and a hard cover plate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged; the chip comprises a functional surface and a non-functional surface opposite to the functional surface, and the non-functional surface of the chip is installed on the first surface of the substrate; the filling material is arranged on the first surface of the substrate and surrounds the chip; thehard cover plate covers the functional surface of the chip; and the chip, the substrate, the filling material and the hard cover plate have mutually matching thermal expansion coefficients. Comparedwith the prior art, the packaging structure can reduce the warpage of the chip.

Description

technical field [0001] The invention relates to a chip package structure and a method for constructing the package structure, in particular to the field of thermally packaged chips. Background technique [0002] During the packaging process of the chip, the substrate with the chip fixed is placed in the lamination equipment, and the encapsulation fluid is injected or melted into the lamination equipment to form a fluid encapsulation chip and the substrate are cooled to form an encapsulation module. In some application requirements It is necessary to cover the surface of the packaging module with a hard cover. In the existing packaging method, the hard cover plate on the surface of the chip uses an adhesive to combine the hard cover plate with the surface of the chip, and then bakes at a high temperature to cure the adhesive. [0003] The disadvantages of the current encapsulation method are: [0004] 1. The process speed is slow and the efficiency is low, and the steps i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L21/56
CPCH01L21/561H01L23/3121H01L23/3142H01L21/56H01L23/31
Inventor 李扬渊皮孟月
Owner MICROARRAY MICROELECTRONICS CORP LTD
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