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A Stability Fault Test Method for Low Voltage SRAM

A fault testing, low-voltage technology, applied in static memory, instruments, etc., can solve problems such as inaccurate detection of stability faults, high-voltage reading is not allowed, and low accuracy, etc., to achieve ingenious design and improve detection sensitivity , high precision effect

Active Publication Date: 2020-07-31
NANJING UNIV OF POSTS & TELECOMM +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] However, for low-voltage SRAM, the write path is different from the read path, and the read operation only turns on its read word line, not the write word line. The read operation in the RES scheme cannot attack the stored data and detect stability failures. , due to the high test time overhead, high-voltage reading after low-voltage writing is not allowed; moreover, the low-voltage writing / high-voltage reading scheme cannot accurately detect stability faults, and there is a problem of low accuracy

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  • A Stability Fault Test Method for Low Voltage SRAM
  • A Stability Fault Test Method for Low Voltage SRAM
  • A Stability Fault Test Method for Low Voltage SRAM

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Embodiment Construction

[0035] The present invention will be further described below in conjunction with the accompanying drawings.

[0036] The stability failure testing method for low-voltage SRAM of the present invention comprises the following steps,

[0037] Step (A), adding a test circuit on the low-voltage SRAM to form the floating 0 and floating 1 required by the bit line BLB of the low-voltage SRAM in the test mode. The test circuit includes transistor M1, transistor M2, and a non-gate device I1 And AND gate device I2,

[0038] The transistor M1 is connected to the precharging loop of the bit line BLB, the NOT gate device I1, the AND gate device I2, and the transistor M1 are sequentially connected to the discharge loop of the bit line BLB, the source of the transistor M1, the AND gate device One input terminal of I2 is connected to the control signal input terminal A1, and the control signal input terminal A1 is set to 0 or 1 to control the on-off of the transistor M1, the transistor M2, th...

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Abstract

The invention discloses a stability fault testing method for low-voltage SRAM. A test circuit is added to the low-voltage SRAM to form the floating 0 and floating 1 required by the bit line BLB of the low-voltage SRAM in the test mode, which can be accurately measured Stability faults in low-voltage SRAM cells. At the same time, by injecting stability faults into low-voltage SRAMs and attacking the low-voltage SRAMs by adding test circuits, it is possible to avoid interference with internal low-voltage SRAMs and reduce The minimum detectable resistance for stability faults between cross-coupled transistors and power or ground, in order to achieve the purpose of improving detection sensitivity, the test method, high precision, ingenious design, has a good prospect.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuit testing, in particular to a stability fault testing method for low-voltage SRAM. Background technique [0002] The rapid development of mobile Internet applications has put forward higher and higher requirements for the processing power and battery life of smart mobile devices. Static Random Access Memory (SRAM) is one of the key modules of mobile processors. SRAM is fast, small in capacity, and has good compatibility. It is generally used as embedded memory, that is, cache or temporary storage device. [0003] In order to meet the ever-increasing performance and power consumption requirements, the design of low-voltage SRAM is gradually becoming a research hotspot in the industry. In order to improve the overall performance of the system on chip, reducing the power supply voltage is an effective means to improve the energy efficiency index of the circuit. However, when the po...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 荣佑丽郭艳艳王昌强王荧蔡志匡
Owner NANJING UNIV OF POSTS & TELECOMM