FPGA (Field-Programmable Gate Array) self test method and device

A technology of self-test and test files, which is applied in the field of FPGA self-test, can solve the problems of automatic test, such as large amount of saved data, low efficiency, and test FPGA logic circuit, etc., to achieve the effect of narrowing the scope of problem location, improving location efficiency, and improving test speed

Inactive Publication Date: 2018-07-10
ZTE CORP
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0005] According to the technical problem solved by the solution provided by the embodiment of the present invention, it is impossible to test the FPGA logic circuit in the real operating environment, and the automated test saves a lot of data and the efficiency is low

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  • FPGA (Field-Programmable Gate Array) self test method and device
  • FPGA (Field-Programmable Gate Array) self test method and device
  • FPGA (Field-Programmable Gate Array) self test method and device

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Embodiment Construction

[0038] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0039] figure 1 It is a flow chart of a method for FPGA self-test provided by the embodiment of the present invention, such as figure 1 shown, including:

[0040] Step S101: The test single board configured with an FPGA chip and capable of running an FPGA program receives the FPGA test file and the FPGA version sent by the PC;

[0041] Step S102: the test board generates an FPGA test version capable of running the FPGA test file by loading and running the FPGA version;

[0042] Step S103: the test single board forms a plurality of functional units capable of automatically executing each test task in the FPGA test file by running the FPGA test version, a...

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Abstract

The invention discloses a FPGA (Field-Programmable Gate Array) self test method and device, which relate to the technical field of electronic and automatic test. The method comprises steps: a test single board configured with an FPGA chip and capable of operating an FPGA program receives an FPGA test file sent by a PC and an FPGA version; through loading operation of the FPGA version, the test single board generates an FPGA test version capable of operating the FPGA test file; and through operating the FPGA test version by the test single board, multiple function units for automatically executing various test tasks in the FPGA test file are formed, test is performed, and the test results are returned to the PC. Self test on an FPGA logic circuit in a real scene and a real processing time sequence can be carried out, and the self test result is more credible.

Description

technical field [0001] The invention relates to the technical field of electronics and automatic testing, in particular to a method and device for FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) self-testing. Background technique [0002] Due to its rich interface resources and flexible and fast programmable features, FPGA can customize a dedicated integrated circuit to make up for the lack of commercial chips and meet the special functional requirements of users. Therefore, it has a wide range of applications in communication, multimedia, information processing and other fields. [0003] In the development and application of FPGA, the test and verification of logic function is a very important step. Traditional FPGA testing and verification is mainly done through simulation. Commonly used simulation methods include: using simulation tools integrated into compilation software provided by FPGA manufacturers, or using special simulation tools developed by ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3185
CPCG01R31/2851G01R31/318519
Inventor 王敬美许乐汤建新何勃
Owner ZTE CORP
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