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Interference testing method for SONOS flash

A test method and disruptive technology, applied in static memory, instruments, etc., can solve the problems of non-operating line influence, long test time, etc., and achieve the effect of reducing test time, improving test rate and saving test cost

Active Publication Date: 2018-07-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] As far as 95nm embedded (Embedded) SONOS flash memory (Flash) is concerned, there is a self-interfering test problem, which is mainly manifested in the main area, that is, the continuous operation of individual rows in the storage array will affect other non-operating rows, and at certain temperatures under the obvious
Existing intrusive test methods for SONOS flash memory require long test times

Method used

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  • Interference testing method for SONOS flash

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Embodiment Construction

[0022] Such as figure 1 Shown is a flowchart of a method according to an embodiment of the present invention. The interference test method for a SONOS flash memory according to an embodiment of the present invention includes the following steps:

[0023] Step 1: Provide a SONOS flash memory that needs to be tested for interference, and adjust and set interference degradation parameters.

[0024] In the embodiment of the present invention, the interference degradation parameters include: positive voltage (VPOS), negative voltage (VNEG), reference voltage (VREF), and bit line voltage (VBL).

[0025] The storage array of the SONOS flash memory has a NOR structure.

[0026] The storage array of the SONOS flash memory is a main area, and a peripheral circuit is also provided on the outer periphery of the main area, and a charge pump is provided in the peripheral circuit. The voltage corresponding to the interference degradation parameter is provided by the voltage pump of the SONOS flash ...

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Abstract

The invention discloses an interference testing method for an SONOS flash. The interference testing method comprises the following steps: step 1, providing the SONOS flash needing the interference test, setting the interference degradation parameters; step 2, continuously operating a target storage unit of the SONOS flash according to the set interference degradation parameters; step 3, testing the threshold voltage of the adjacent storage unit, and screening the adjacent storage unit whose threshold voltage is out of scope. The interference degradation parameters are set before the continuousoperation, the continuous operation is carried out according to the interference degradation parameters, the adjacent storage unit is rapidly interfered and degraded in the continuous operation, so that the time for the continuous operation is saved, the testing time is finally shortened, the testing speed is increased, and the testing cost is saved.

Description

Technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for testing interference of SONOS flash memory. Background technique [0002] In addition to guaranteeing the functional characteristics of semiconductor devices, reliability evaluation is also an important guarantee, which is an important guarantee for the stable and durable use of the device. [0003] The so-called reliability evaluation refers to the ability of a product to complete a specified function under specified conditions and within a specified time. In the process of design and application, the product is constantly subjected to the influence of itself and the external climate environment and mechanical environment, but still needs to be able to work normally, which needs to be verified by test equipment. The current reliability evaluation of memory mainly includes endurance test (ENDURANCE), data retention test (DATA RETENTION), and ...

Claims

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Application Information

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IPC IPC(8): G11C29/08
CPCG11C29/08
Inventor 孙黎瑾宋旻皓陈斌斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP