Defect scanning method and scanning device for semiconductor device
A defect scanning and scanning device technology, applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as slow speed, and achieve the effect of simple device, fast and high-precision focusing
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Embodiment 1
[0084] The defect scanning method of the present invention is described in detail below with reference to the accompanying drawings; figure 2 shows a process flow diagram of the defect scanning method of the present invention; Figures 3A-3C A schematic structural view of the microlens array of the present invention is shown; Figures 4A-4B A schematic diagram of the working principle of the microlens array of the present invention is shown; Figure 5 A schematic diagram showing the principle of coherence of the microlens array of the present invention; Figure 6 It shows a schematic diagram of the step-by-step alignment of the microlens array of the present invention; Figure 7 A schematic diagram of precise alignment of the microlens array of the present invention is shown.
[0085] The invention provides a defect scanning method of a semiconductor device, such as figure 2 As shown, the main steps of the method include:
[0086] Step S1: providing a wafer to be inspec...
Embodiment 2
[0134] The present invention also provides a defect scanning device for a semiconductor device, the scanning device comprising:
[0135] A microlens array, arranged above the wafer to be inspected, for imaging the wafer to be inspected;
[0136] The focusing device is arranged on the edge of the micro-lens array, and is used to focus the micro-lens array within the range of the detection distance step by step through wide-spectrum light source interferometry.
[0137] Wherein the wafer to be inspected may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, including these semiconductors The multi-layer structure composed of silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI) )Wait.
[0138] Wherein, various devices can be formed in the wafer to be inspected, for exampl...
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Abstract
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