Anti-interference method for DRAM controller and circuit and chip

Abstract

The invention relates to an anti-interference method for a DRAM controller and a circuit and a chip. The method comprises the steps that a DQS time window signal is used to filter out a glitch locatedout of the time window segment in the DQS signal, so that a more accurate DQS signal is obtained, and the anti-interference property of the DRAM controller is improved. The anti-interference circuitand chip not only can filter out the glitch of the DQS signal, but also can compare the pulse quantity with emergency quantity of the corresponding DQS signal in the time window segment, if the numbers of the pulse quantity and emergency quantity are same, it is suggested that the DQS signal is a valid signal, a DQS processing module sends a control signal to a reading data acquisition module to make the reading data acquisition module perform the reading data acquisition operation; if the numbers of the pulse quantity and emergency quantity are different, it is suggested that the DQS signal is abnormal and is an invalid signal, the DQS processing module sends a control signal to a command sending module to make the command sending module send a reading command again to a DRAM, and the DRAM returns the data again after receiving the command.

Description

technical field [0001] The invention relates to the field of digital circuits, in particular to an anti-interference method, circuit and chip of a DRAM controller. Background technique [0002] Existing processors or SOCs (System on Chip, referred to as System on Chip) are more or less limited by memory access performance, and the memory wall problem is becoming more and more obvious. In a SOC system, DRAM (Dynamic Random Access Memory), that is, dynamic random access memory, is the fastest external memory, and the fastest DRAM speed can reach more than 1GHz. At such a fast speed, noise and interference have a great impact on DRAM, which can easily lead to DRAM read and write errors. In the communication between DRAM and memory controller, DQS (data selection pulse) is mainly used to accurately distinguish each transmission cycle within one clock cycle, and to facilitate the receiver to receive data accurately. If the DQS itself has many glitches and other disturbances, it...

AI Technical Summary

Problems solved by technology

If DQS itself has a lot of interference such as glitches, it is more likely to cause DRAM read and write errors

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