Successive Approximation Analog-to-Digital Converter Based on Code Value Estimation

Abstract

The invention relates to a successive approximation analog-to-digital converter based on code value estimation, which belongs to the field of semiconductor integrated circuits. The existing successive approximation analog-to-digital converter needs to make a judgment bit by bit from MSB to LSB, and it takes N+1 clock cycles to complete a conversion. The successive approximation analog-to-digital converter based on code value estimation technology can achieve jump The bit judgment cycle of the high-bit capacitor reduces the number of clock cycles required for a conversion, greatly reduces power consumption, and improves the conversion speed. The present invention roughly estimates the digital code obtained in the next conversion cycle through the code value estimation, and can skip the bit judgment cycle of the high-bit capacitor, so as to improve the conversion speed and reduce power consumption.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and relates to a successive approximation analog-to-digital converter based on code value estimation. Background technique [0002] The circuit structure of the traditional successive approximation analog-to-digital converter (SARADC) is as follows: figure 1 As shown, an N-bit SARADC includes N binary weight capacitors. During the sampling phase, the switch connected to the input signal Vip and Vin in the switch S1 is turned on, and the switch S2 is turned on. The upper plate of the capacitor is connected to the input signal, and the lower plate is connected to the input signal. The plate is connected to the common mode level, and after the sampling is completed, it enters the conversion phase. The switch connected to the input signal Vip and Vin in the switch S1 is turned off, the switch S2 is turned off, and the lower plate of the capacitor is floating. According to the comparis...

AI Technical Summary

Problems solved by technology

[0002] The circuit structure of the traditional successive approximation analog-to-digital converter (SARADC) is as follows: figure 1 As shown, an N-bit SARADC includes N binary weight capacitors. During the sampling phase, the switch connected to the input signal Vip and Vin in the switch S1 is turned on, and the switch S2 is turned on. The upper plate of the capacitor is connected to the input signal, and the lower plate is connected to the input signal. The plate is connected to the common mode level, and after the sampling is completed, it enters the conversion phase. The switch connected to the input signal Vip and Vin in the switch S1 is turned off, the switch S2 is turned off, and the lower plate of the capacitor is floating. According to the comparison result of the comparator, it is successively approximated The logic determines the level connected to the upper plate of the capacitor bit by bit from the high bit to the low bit. It can be seen from the working process that at least N+1 clock cycles are required to complete a conversion. Each clock cycle corresponds to a capacitor charging and discharging, which limits the While the conversion speed of the ADC is high, the power consumption is also large

Images