Single-chip microcomputer system resisting latch-up effect

Abstract

The invention discloses a single-chip microcomputer system resisting latch-up effect, and relates to the technical field of electronic engineering. In the design of a power supply circuit in the system, from selection of a power source to design of a power supply filter, the external single-chip microcomputer locking triggering risk caused in the power supply aspect is eliminated; in the design ofa clock circuit, from selection of a clock frequency to layout of a clock circuit, the external single-chip microcomputer locking triggering risk caused in the high frequency clock signal aspect is eliminated; in the design of a reset circuit, a reset circuit designed by a light triggered mechanism is adopted, and has shared power supply and isolated power supply application compatibility, so that power supply detection and a leakage flow channel are linked in time, and the single-chip microcomputer locking triggering risk caused by a reset signal is effectively avoided; high priority interruption and a leakage flow channel are linked in time, data safety is ensured, output ports are switched off in order, and the external forming condition of the locking effect of the single-chip microcomputer is effectively disintegrated; and an effective I / O port application method is adopted, and the external single-chip microcomputer locking triggering risk in the I / O port aspect is eliminated.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to an anti-latch effect single-chip microcomputer system. Background technique [0002] The advantages of CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) technology, such as low power consumption, non-proportional logic design, and large noise margin, make it a digital circuit, an analog circuit, and a mixed analog and digital circuit on the same chip. preferred technology for circuits. However, the parasitic bipolar transistor inherent in the CMOS structure will be activated under certain conditions, forming a positive feedback and generating a latch, causing the IC (integrated circuit, integrated circuit) circuit to malfunction, causing data or logic state changes, data If it is lost, it will even burn the chip in severe cases, resulting in permanent failure of the circuit. [0003] The current IC layout process design can basically av...

AI Technical Summary

Problems solved by technology

Modern CMOS circuits, especially various microprocessor applications represented by embedded control, are growing geometrically. In the process of prototype debugging and system application, various errors such as software runaway, data loss, and parameter changes often occur. , When solving this kind of problem, eliminate the error of the software itself. Due to the diversity and complexity of the actual application circuit and the external environment, many engineers still have problems after taking quite a lot of measures to avoid latch-ups mentioned above.

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