SRAM memory and formation method

A memory and latch technology, applied in the direction of electric solid state devices, semiconductor devices, electrical components, etc., can solve problems such as poor electrical performance of static random access memory, and achieve the effect of improving speed

Inactive Publication Date: 2018-08-31
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the electrical perfor

Method used

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Examples

Experimental program
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Example Embodiment

[0032] As mentioned in the background art, the electrical performance of the SRAM memory formed by the prior art is poor.

[0033] figure 1 is a circuit diagram of an SRAM memory cell, the SRAM memory cell includes a pass transistor, a pull-up transistor and a pull-down transistor, the pass transistor includes a first pass transistor PG1 and a second pass transistor PG2, and the pull-up transistor includes a first pass transistor PG1 and a second pass transistor PG2. A pull-up transistor PU1 and a second pull-up transistor PU2, the pull-down transistors include a first pull-down transistor PD1 and a second pull-down transistor PD2, and the pull-up transistor and the pull-down transistor form a latch. Refer to the connection relationship of the pass transistor, pull-up transistor and pull-down transistor figure 1 .

[0034]When reading data "0", the current in PD1 needs to be greater than the current in PG1, otherwise the data "0" cannot be read correctly; when writing data "...

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Abstract

A SRAM memory and a formation method are disclosed. The method comprises the following steps of providing a substrate; forming a transmission transistor, wherein the method of forming the transmissiontransistor includes: forming a transmission grid structure on the substrate; the substrate of the bottom of the transmission grid structure possesses a channel region; and the transmission grid structure has a first side and a second side which are opposite to each other; forming a first stress layer in the substrate of the first side of the transmission grid structure, wherein a first distance is arranged between the bottom surface of the first stress layer and the bottom surface of the transmission grid structure; and forming a second stress layer in the substrate of the second side of thetransmission grid structure, wherein the materials of the second stress layer and the first stress layer are the same, a second distance is arranged between the bottom surface of the second stress layer and the bottom surface of the transmission grid structure, and the second distance is less than the first distance. By using the method, the electrical performance of the SRAM memory is increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SRAM memory and a forming method thereof. Background technique [0002] With the continuous development of semiconductor technology, memory presents a development trend of high integration, high speed, and low power consumption. [0003] Functionally, memory is divided into random access memory (RAM, Random Access Memory) and read-only memory (ROM, Read Only Memory). When the random access memory is working, data can be read from any specified address at any time, and data can also be written to any specified storage unit at any time. The read and write operation of the random access memory is convenient and the use is flexible. [0004] Random access memory can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Among them, SRAM utilizes flip-flops with positive feedback to store data, and mainly relies on continuous power ...

Claims

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Application Information

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IPC IPC(8): H01L27/11H01L29/06H01L29/78
CPCH01L29/0603H01L29/7842H10B10/12
Inventor 甘正浩冯军宏
Owner SEMICON MFG INT (SHANGHAI) CORP
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