Double Rate Synchronous DRAM

Abstract

The embodiment of the invention provides a double data rate synchronous dynamic random access memory. The double data rate synchronous dynamic random access memory comprises a first control pulse generating circuit and a column address strobe pulse delay circuit; the first control pulse generating circuit is used for generating a first control pulse according to a received column address strobe pulse so that the first control pulse and the column address strobe pulse can conform to a preset logic function, wherein one column address strobe pulse corresponds to one preset clock cycle; the column address strobe delay circuit is connected with the first control pulse generating circuit so as to receive the first control pulse; the column address strobe pulse delay circuit is used for receiving a first command, and delaying the first command according to the first control pulse so as to obtain a second command; the delayed clock cycle and the difference value of decimal number corresponding to the first control pulse are the same, and the delayed clock cycle of the second command relative to the first command is equal to the preset clock cycle corresponding to the column address strobepulse. The random access memory is relatively simple in structure.

Description

technical field [0001] The invention relates to a dynamic random access memory, in particular to a double rate synchronous dynamic random access memory. Background technique [0002] The column address strobe (column address strobe, referred to as CAS) controls the interval time from receiving the command to executing the command, that is, the delay time. The column address strobe delay time is the length of the delay time from the receipt of the command to the execution of the command controlled by the column address strobe, and it is also one of the important indicators to measure the memory that supports different specifications at a certain frequency. [0003] The double-rate synchronous DRAM usually uses the column address strobe set by the register to directly control the column address strobe delay circuit. Since the binary number represented by each binary column address strobe pulse read by the register changes continuously, the number of clock cycles of the delay ...

AI Technical Summary

Problems solved by technology

In this way, the design of the column address strobe delay circuit should consider the discontinuous control, so the design of the column address strobe delay circuit becomes complicated, resulting in a complex structure and a large area of ​​the column address strobe delay circuit, which leads to memory loss. The structure is complex, the area is large and the power consumption is large

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