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Interleaved parallel PFC circuit

A circuit and parallel technology, applied in the direction of electrical components, high-efficiency power electronic conversion, output power conversion devices, etc., can solve the problems of small output power, large inductance, high current and voltage of switching devices, etc.

Inactive Publication Date: 2018-09-28
任建光
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the present invention provides an interleaved parallel PFC circuit to overcome the traditional power factor correction circuit Boost inductance, small output power, switching devices of the circuit withstand large current and voltage, large current ripple, etc. shortcoming

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Embodiment Construction

[0016] The technical solutions provided by the present invention will be further described below in conjunction with the accompanying drawings.

[0017] In the prior art, improving the power of PFC generally proceeds from the following aspects, one is the application of new power devices; Nowadays, two-stage interleaved parallel power factor correction can handle most applications, and its power can reach 5KW or even higher. For example, the UCC28070 chip produced by TI provides a two-stage interleaved circuit design. However, how to use the existing two-level interleave chip to realize multi-level interleave has become an urgent problem to be solved in the prior art.

[0018] The technical idea of ​​the present invention is to use a synchronous clock signal to combine multiple PFC chips. For example, three UCC28070 chips are separated by providing synchronous signals for chip working periods. Because a single UCC28070 chip provides a two-stage interleaved circuit design, Th...

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Abstract

The invention discloses an interleaved parallel PFC circuit comprising chips U4, U5, U6, resistors R55-R93, and capacitors C20 C51. The Boost PFC circuit of the invention has a small current ripple, thereby reducing the switching device stress and the boost inductor size. By adopting the technical scheme of the invention, the defects of Boost inductance of the conventional power factor correctioncircuit is large, the output power is small, the switching device of the circuit bears large current and voltage, and the current ripple is large and the like can be overcome.

Description

technical field [0001] The invention belongs to the technical field of charging power sources, and relates to a power factor correction of a large-scale and high-power battery charging system, in particular to an interleaved parallel PFC circuit. Background technique [0002] With the widespread use of power electronic devices, because some devices themselves work in a nonlinear state, a large number of harmonics will be generated. When these harmonic currents enter the power system, they will pollute the power grid. In order to comply with the harmonic standard current limit of the IEC61000-4-2 standard proposed by the International Electrotechnical Commission (IEC), in the application of the switching power supply, try to improve its power factor and reduce the harmonic pollution on the power grid. In recent years, with the continuous development of electric vehicles and backup energy storage battery stations, the power required for AC power supply equipment is also increa...

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Application Information

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IPC IPC(8): H02M1/42
CPCH02M1/4216Y02B70/10
Inventor 任建光
Owner 任建光
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