Three-dimensional semiconductor element and manufacturing method thereof

Abstract

The invention discloses a three-dimensional semiconductor element, comprising: a substrate including an array area and a stepped area adjacent to the array area, wherein the stepped area includes N steps, where N is an integer greater than or equal to 1; a stacked layer having A multi-layer structure is stacked on the substrate, and the multi-layer structure includes active layers and insulating layers arranged alternately above the substrate, and the stack includes a plurality of sub-stacks formed on the substrate, and these sub-stacks are connected to the N The steps are correspondingly arranged to form contact areas respectively, wherein an uppermost active layer of each stack in the contact areas includes a metal silicide layer; and multilayer structure connectors are respectively located in the corresponding contact areas, and the multilayer The structural connector extends downward to electrically connect the metal silicide layers of each sub-stack.

Description

technical field [0001] The present invention relates to a three-dimensional semiconductor device and its manufacturing method, and in particular to a three-dimensional semiconductor device with metal silicide and its manufacturing method. Background technique [0002] A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory planes including memory cells to achieve a memory structure with higher storage capacity. For example, some stacked NAND gate (NAND) flash memory structures have been proposed. Relevant practitioners have proposed three-dimensional memory elements with various structures, such as single-gate memory cells, double-gate memory cells, and surrounding g...

AI Technical Summary

Problems solved by technology

However, since the formation of the etch stop layer will affect the contact landing windows (contact landing windows)

If it is necessary to form more pairs of oxide layer-polysilicon layer (commonly referred to as OP layer) stacks when developing a three-dimensional semiconductor device, it is necessary to form a thicker etch stop layer, and this thicker etch stop layer The formation of will have a greater adverse effect on the contact landing window

Furthermore, the presence of the etch stop layer leaves less space for contact landing windows when shrinking the size of 3D semiconductor devices, which poses problems for both process and structure

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