Data mapping system and method for realizing parallel convolution calculation

Abstract

The invention discloses a data mapping system and method for realizing parallel convolution calculation, and belongs to the technical field of neural networks. The data mapping system for realizing parallel convolution calculation of the present invention comprises an input feature cache module, a mapping logic module, an output feature map cache module, a weight cache module, a convolution calculation array and a control logic module, wherein the input feature map cache module is respectively connected with the control logic module and the mapping logic module; the weight cache module is respectively connected with the control logic module and the mapping logic module; the calculation array is connected with the control logic module, the mapping logic module and the output feature map cache module; and the output feature map cache module is connected with the control logic module. The data mapping system for realizing parallel convolution calculation in the invention can eliminate theinvalid or non-participating calculation resource, improves the calculation utilization rate and has good popularization and application value.

Description

technical field [0001] The invention relates to the technical field of neural networks, and specifically provides a data mapping system and method for realizing parallel convolution calculation. Background technique [0002] With the development of the field of artificial intelligence (AI), CNN (Convolutional Neural Network) has been fully utilized. At present, the mainstream convolutional neural network model is not only complex in structure, but also has a large amount of calculation data, and the architecture of each layer is also very different. It is not easy to achieve high performance and high versatility of hardware circuits. Both resource utilization and energy efficiency must be considered. Compare. It is unrealistic to realize all layers of the entire network model with hardware circuits at the same time, and it is difficult to obtain satisfactory results in terms of power consumption, area, and resource utilization. Usually, the solution to this problem is to ex...

AI Technical Summary

Problems solved by technology

At present, the mainstream convolutional neural network model is not only complex in structure, but also has a large amount of calculation data, and the architecture of each layer is also very different. It is not easy to achieve high performance and high versatility of hardware circuits. Both resource utilization and energy efficiency must be considered. Compare

It is unrealistic to realize all layers of the entire network model with hardware circuits at the same time, and it is difficult to obtain satisfactory results in terms of power consumption, area, and resource utilization. Usually, the solution to this problem is to exchange time for area, that is, to divide the entire model into layers Processing, design the circuit as a general-purpose basic unit, construct the entire model by controlling the circuit time-sharing, and improve resource utilization through efficient data mapping methods, thereby improving circuit performance

In the prior art, when the hardware circuit implements some convolutional neural network model calculations, there is a case where the sliding step of the convolution kernel is greater than 1, there is invalid calculation, which reduces the resource utilization rate; on the other hand, the calculation array circuit design is fixed. In some cases, if there is a mismatch between the output feature map and the calculation array size, there will be resources that do not participate in the calculation, and there will be waste of resource utilization. The waste of calculation resources will make the overall performance less than ideal.

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