Fraction-n digital pll capable of canceling quantization noise from sigma-delta modulator

Abstract

A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtereddigital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisyfeedback frequency signal to thereby generate the feedback frequency signal.

Description

technical field [0001] The present disclosure relates to locked loop circuits, such as, for example, fractional-N / integer-N phase-locked loop (PLL) or frequency-locked loop (FLL) circuits, and in particular to methods for eliminating sigma-delta modulation by frequency dividers in locked-loop technology that generates quantization noise in the way. Background technique [0002] Locked loop circuits, such as phase locked loop circuits, are fundamental components of radio, wireless and telecommunications technology. A Phase Locked Loop or Phase Locked Loop (PLL) is a control system that generates an output signal having a phase that is related to the phase of the input signal. A simple PLL consists of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal, and the phase detector compares the phase of the signal to the phase of a reference periodic signal, adjusting the oscillator to maintain a phase match. Keeping the input and outp...

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Problems solved by technology

[0008] Although this implementation provides a digitally implemented fractional-N PLL, the power consumption of this design may be undesirably high due to the TDC 22 and fractional spurs may be generated resulting in undesired performance when generating signals at certain frequencies

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