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Method and system for measuring pattern placement error on wafer

A pattern and wafer technology, applied in the fields of opto-mechanical processing of originals, semiconductor/solid-state device testing/measurement, special data processing applications, etc., which can solve the problem of not detecting PPE, etc.

Pending Publication Date: 2018-11-13
SAMSUNG ELECTRONICS CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although computational lithography simulation can be used to predict PPE, computational lithography simulation does not detect or quantify on-wafer PPE

Method used

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  • Method and system for measuring pattern placement error on wafer
  • Method and system for measuring pattern placement error on wafer
  • Method and system for measuring pattern placement error on wafer

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Embodiment Construction

[0036] In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology will be employed for the sake of clarity. However, the disclosure is not intended to be limited to the specific terms so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.

[0037] Exemplary embodiments of the inventive concepts provide a system and method for detecting and quantifying the degree of pattern placement error (PPE) on a wafer. By detecting and quantifying PPE on the wafer, fabrication can be fine-tuned to minimize PPE, increasing fabrication yield and minimizing waste.

[0038] figure 1 is a flowchart illustrating a method for detecting and quantifying PPE according to an exemplary embodiment of the present inventive concept. Figure 2A , 2B and 2C are schematic diagrams illustrating a system for detecting and quantifying PPE according to an exemplary embodim...

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Abstract

A method for measuring pattern placement error (PPE) on a wafer includes receiving a photomask pattern. One or more unit cell patterns are added to the photomask pattern. Each of the unit cell patterns includes at least one reference design pattern and at least one PPE check design pattern. A photomask is fabricated from the photomask pattern with the one or more unit cell patterns added thereto.A wafer is patterned using the fabricated photomask. A microscope image of the patterned wafer is acquired. Pattern placement error is measured as a displacement between the at least one reference design pattern and the at least one PPE check design pattern.

Description

[0001] Cross References to Related Applications [0002] This application is based on Provisional Application Serial No. 62 / 490,330, filed April 26, 2017, the entire contents of which are incorporated herein by reference. technical field [0003] The present disclosure relates to pattern placement errors, and more particularly, to a method and system for measuring pattern placement errors on a wafer. Background technique [0004] In the field of semiconductor manufacturing, circuits are often created on semiconductor wafers by a photolithographic process in which a photomask (also called a reticle) is used for example using extreme ultraviolet (EUV) light to direct Wafers provide specific exposures. Subsequent processes can etch away exposed areas (or non-exposed areas) of the wafer to create patterns on the wafer. [0005] Typically, semiconductors are fabricated using multiple photomasks (and multiple exposures), so it is important to properly align the exposures from ea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/76G03F1/84G03F7/20
CPCG03F1/76G03F1/84G03F7/7085H01L22/30G03F1/44G03F7/70616G03F7/70683H01L22/12G03F7/706G03F9/7061G03F7/705H01L21/0274H01L27/0203G06F30/20G06F30/392
Inventor 金庆燮
Owner SAMSUNG ELECTRONICS CO LTD
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