FPGA-based Tiny-yolo convolutional neural network hardware acceleration method and system

A convolutional neural network and hardware acceleration technology, applied in the field of convolutional neural network hardware acceleration, can solve the problems of large data transmission overhead, reducing network processing speed, floating-point data occupying hardware platform storage resources, etc.

Active Publication Date: 2018-11-13
CHONGQING UNIV
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Problems solved by technology

[0006] 1: The input and output of each layer of the Tiny-yolo convolutional neural network and the network weight are all floating-point data. During convolution calculation, data caching and data transmission, floating-point data will occupy a large amount of storage resources on the hardware platform.
[0007] 2: The Tiny-yolo convolutional neural network uses a single-channel input method, and the data of each channel is input one by one, which greatly limits the processing speed of the network
[0008] 3: The convolution calculation of the Tiny-yolo convolutional neural network is performed serially. This calculation method leads to a very slow convolution calculation speed and reduces the processing speed of the network.
[0009] 4: During the detection process of the Tiny-yolo convolutional neural network, the pooling operation needs to be performed after the convolution operation is completed, and there is a large data transmission overhead between the two

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  • FPGA-based Tiny-yolo convolutional neural network hardware acceleration method and system

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Embodiment Construction

[0059] The present invention analyzes the parallel features of the Tiny-yolo network and combines the parallel processing capability of the hardware (ZedBoard) to accelerate the hardware of the Tiny-yolo convolutional neural network from three aspects: input mode, convolution calculation, and pooling embedding. Use the HLS tool to design the corresponding IP core on the FPGA to implement the acceleration algorithm, and realize the acceleration of the Tiny-yolo convolutional neural network based on the FPGA+ARM dual-architecture ZedBorad test.

[0060] see Figure 1 to Figure 6 , an FPGA-based Tiny-yolo convolutional neural network hardware acceleration method, comprising the following steps:

[0061] Based on the ZedBoard hardware resources, the convolutional layer conv1-8 of the Tiny-yolo convolutional neural network in this embodiment adopts a dual-channel input mode. On other hardware platforms, due to different resources, the number of channels input at the same time can b...

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Abstract

The invention discloses an FPGA-based Tiny-yolo convolutional neural network hardware acceleration method and system. By analyzing the parallel characteristics of a Tiny-yolo network, and in combination with the parallel processing capability of hardware, the hardware acceleration is carried out on the Tiny-yolo convolutional neural network. The acceleration scheme is used for performing acceleration improvement on the Tiny-yolo network from three aspects that (1) the processing speed of the Tiny-yolo network is increased through multi-channel parallel input; (2) the convolution computing speed of the Tiny-yolo network is increased through parallel computing; and (3) the pooling process time of the Tiny-yolo network is shortened through pooling embedding. The method greatly increases the detection speed of the Tiny-yolo convolutional neural network.

Description

technical field [0001] The invention relates to the technical field of convolutional neural network hardware acceleration, in particular to an FPGA-based Tiny-yolo convolutional neural network hardware acceleration method and system. Background technique [0002] Convolution Neural Network (CNN) is widely used in the field of computer vision, especially in object detection and image recognition, showing good application prospects. Edge computing is a brand-new computing model whose concept is to process data directly at the edge near the data center without sending it back to the server for processing. The use of edge computing in target detection can bring a series of benefits: directly process the image on the hardware device at the acquisition end without sending it back to the host computer, saving data transmission time and reducing data transmission overhead. It is of great practical significance to realize efficient processing on hardware devices by optimizing and ac...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06T1/20G06T1/60
CPCG06N3/063G06T1/20G06T1/60
Inventor 黄智勇吴海华李渊明虞智
Owner CHONGQING UNIV
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