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In situ quantum error correction

An error correction and error technology, applied in error detection/correction, quantum computer, generation of response errors, etc., can solve the problems of not being able to guarantee the best performance of error correction circuits, increasing the complexity of optimization processing, etc.

Active Publication Date: 2022-04-15
GOOGLE LLC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Characterization methods such as random benchmarking or tomography require interruption of necessary error detection operations and do not guarantee optimal performance in error correction circuits
Using error model optimization methods to optimize physical gate parameters requires training an error model so that measured physical errors can be related to physical gates and requires that determined errors be related to changes in control parameters, which adds to the complexity of the optimization process

Method used

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  • In situ quantum error correction
  • In situ quantum error correction
  • In situ quantum error correction

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Embodiment Construction

[0036] This specification describes the quantum system and method, and the error correction operation on the quantum system is running while continuously and efficiently optimizing the quantum performance. The method directly monitors the output from the error detection and provides this information as feedback to calibrate the quantum door associated with the quantum system. In some embodiments, the physical quantum bit is divided into one or more independent hardware patterns (ie, configured) in space, which can be attributed to the error of each hardware mode. One or more different collections of the hardware mode are then temporarily interlaced, allowing all physical quantum bits and operations to be optimized. The method allows for individual and parallel optimizations for each portion of the hardware mode, and can cause O (1) to scale.

[0037] Example operating environment

[0038] Figure 1AIt is a one-dimensional display of an example error correction system 100 for repea...

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Abstract

Methods, systems and apparatus for parallel optimization of continuously running quantum error correction via closed-loop feedback. In one aspect, a method includes continuously and efficiently optimizing qubit performance in situ while error correction operations on the quantum system are running. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware modes, where errors attributable to each hardware mode are non-overlapping. One or more different sets of hardware patterns are then temporally interleaved such that all physical qubits and operations are optimized. This approach allows the optimization of each part of the hardware pattern to be performed separately and in parallel, and can result in O(1) scaling.

Description

Technical field [0001] This specification relates to quantum calculations, and more particularly to quantum level performance in quantum calculations. Background technique [0002] Constructing a fault tolerance quantum computer requires optimizing physical gate parameters. The characterization method such as a random base test or fault scan requires an interrupt necessary error detection operation and does not guarantee the best performance in the error correction circuit. Use the error model optimization method to optimize the physical gate parameter requirements training error model, so that the measured physical error can be associated with the physical gate, and the determined error is associated with the change of the control parameters, which increases the complexity of the optimized processing. Inventive content [0003] This specification describes techniques related to the continuous and parallel optimization of quantum performance in the runtime, where the error corre...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N10/70G06N10/40H10N60/80
CPCG06N10/70G06N10/40G06N10/20G06N10/60B82Y10/00H01L29/66977G06N99/00G06F11/0751H10N60/805G06F11/0787G06F11/08
Inventor J.S.凯利
Owner GOOGLE LLC