Semiconductor structure and operation method thereof

Abstract

A semiconductor structure includes a first guard ring and a second guard ring. The first guard ring is positioned in the substrate. The first guard ring includes a plurality of first doped regions anda plurality of second doped regions that are all arranged alternately. The first doped regions and the second doped regions are mutually different in conductivity types. The second guard ring is positioned beside the first guard ring. The second guard ring includes a plurality of third doped regions, a plurality of fourth doped regions and a plurality of mask layers, wherein the third doped regions and the fourth doped regions are alternately arranged. All of the third doped regions correspond to all of the second doped regions through one to one correspondence. All of the fourth doped regions correspond to all of the first doped regions through one to one correspondence. The third doped regions and the first doped regions are the same in conductivity type and are arranged in a staggered.The mask layers are respectively disposed on the substrate between the third doped regions and the fourth doped regions.

Description

technical field [0001] The present invention relates to a semiconductor structure and its operation method, and in particular to a semiconductor structure with electrostatic discharge (ElectroStatic Discharge, ESD) protection capability and its operation method. Background technique [0002] Electrostatic discharge (ESD) is a phenomenon in which charge accumulates on a non-conductor or an ungrounded conductor, and then travels rapidly and discharges in a short period of time through the discharge path. Electrostatic discharge can cause damage to circuits in integrated circuits. For example, a human body, a machine for packaging integrated circuits, or an instrument for testing integrated circuits are all common charged objects. When the above-mentioned charged objects come into contact with the chip, it is possible to discharge the chip. The instantaneous power of electrostatic discharge can cause damage or failure of the integrated circuits in the chip. [0003] Because i...

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Problems solved by technology

However, the current only flows through the MOS surface with low on-state resistance, which makes the ESD discharge path limited and it is not easy to improve ESD performance

In addition, a MOS with a high breakdown voltage (Breakdown Voltage, BV) also has a high trigger voltage (Trigger Voltage), which increases the risk of MOS damage

In the field of power semiconductor components, the above two considerations are a great challenge in improving the effectiveness of ESD protection

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