Semiconductor structure, memory structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure, a memory structure and a manufacturing method thereof. The method comprises the following steps: 1) a semiconductor substrate is provided; 2) a word line is formed in the semiconductor substrate; 3) a bit line is formed on the semiconductor substrate; 4) a filling dielectric layer is formed on the semiconductor substrate; 5) a graphical mask layeris formed on the filling dielectric layer; 6) a side wall oxide layer is formed on the graphical mask layer; 7) a graphical etching barrier layer is formed on the structure obtained in the step 6); 8)a first isolation through hole and a second isolation through hole are formed in the filling dielectric layer; 9) a first graphical unit, a second graphical unit and a side wall oxide layer below thesecond graphical unit are removed; 10) a first insulation isolation structure is formed in the first isolation through hole, and a second insulation isolation structure is formed in the second isolation through hole; and 11) the filling dielectric layer is removed, and a conductive plug is formed. The conductive plug can realize reduction of contact resistance between the conductive plug and an active region.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor structure, a memory structure and a preparation method thereof. Background technique [0002] With the development of technology, the size of the conductive plug used to electrically connect the functional devices in the semiconductor substrate with the outside in the semiconductor structure is getting smaller and smaller, so that the conductive plug is prone to offset, and the conductive plug and the active region The effective contact area becomes smaller, for example, Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM for short) is composed of many repeated storage units. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor. Each transistor includes a gate and a source and drain located in the substrate. The source / drain is connected to the bit line. , and the drain / ...

AI Technical Summary

Problems solved by technology

With the development of technology, the size of the DRAM shrinks, and the feature size and cell area of ​​the DRAM decrease accordingly, which makes it easy for the formed conductive plug to shift, so that the conductive plug The effective contact area between the plug and the active region in the semiconductor substrate becomes smaller, so that the contact resistance between the conductive plug and the active region and the resistance of the conductive plug itself are relatively large

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