Digital assisted locking circuit

Abstract

The invention relates to the field of radio frequency integrated circuit design, in particular to a digital auxiliary locking circuit, comprising a locking detection circuit and a control circuit, wherein the locking detection circuit is used for detecting a phase difference between a reference signal and a feedback signal from a frequency dividing circuit, and transmitting the phase difference signal to the control circuit. The control circuit is electrically connected to the frequency dividing circuit to receive a target frequency dividing signal transmitted by the frequency dividing circuit. The control circuit is electrically connected to the lock detection circuit to receive a phase difference signal sent by the lock detection circuit. This circuit reduces the number of times of the feedback-adjustment of phase locked loop (PLL), can effectively reduce the PLL loop lock time, to achieve the PLL fast lock function.

Description

technical field [0001] The invention relates to the field of radio frequency integrated circuit design, in particular to a digital auxiliary locking circuit of a phase-locked loop. Background technique [0002] PLLs can generate precise clock signals or frequency signals, so they are widely used in circuit systems such as clock generators, wireless communication systems, and clock / data recovery circuits. Frequency synthesizers based on phase-locked loops are widely used in radio frequency transceiver systems. These requirements have promoted the research and development of phase-locked loop circuits. [0003] The locking time of the phase-locked loop is an important parameter to characterize the performance of the phase-locked loop. The length of the locking time directly affects the response time of the transceiver system. If the locking time is too long, the working time of the modules in the system will be extended, which will lead to excessive power consumption of the s...

AI Technical Summary

Problems solved by technology

[0003] The locking time of the phase-locked loop is an important parameter to characterize the performance of the phase-locked loop. The length of the locking time directly affects the response time of the transceiver system. If the locking time is too long, the working time of the modules in the system will be extended, which will lead to excessive power consumption of the system.

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