A Time Interval Measurement Method Based on Multiple Sampling

Abstract

The invention provides a time interval measurement method based on multiple sampling. The method provided by the invention comprises the following steps: inputting two input signals into two identicaldelay rings separately to transmit the signals in the delay rings, the two input signals being a Start signal and a Stop signal; sampling the Start signal and the Stop signal using a sampling clock smaller than a delay ring period by a fixed value tau; and calculating to obtain a time interval between the two input signals based on times of cycles of the Start signal and the Stop signal transmitted in the delay rings at the end of the sampling and positions of the signals in the rings. The technical scheme provided by the invention solves the problem of low measurement precision of existingtime-to-digital converters and can be applied more widely.

Description

technical field [0001] The present invention relates to the technical field of integrated circuit design, in particular, to a time interval measurement method based on multiple sampling. Background technique [0002] With the wide application of high-precision measurement in various fields, its status is getting higher and higher. Whether it is the traditional high-precision measurement of time or the digital system design based on the time-to-digital converter in recent years, it is required that the time-to-digital converter has a higher resolution to achieve higher measurement accuracy. The time-to-digital converter uses the delay effect of the logic circuit unit to quantify the output of the time interval between two input signals according to a certain accuracy, and realizes the time-to-digital conversion to achieve high-precision measurement of the time interval. The application range of high-resolution time-to-digital converters mainly includes high-energy physics, m...

AI Technical Summary

Problems solved by technology

However, these structures have their own problems. For example, in a time-to-digital converter with a vernier delay chain structure, the size of the on-chip mismatch in a specific process will limit the value of the delay difference, thereby limiting the resolution. At the same time, its dynamic range and delay There is a contradiction in the length of the chain

The disadvantage of the time-to-digital converter in the ring structure is that the time resolution is limited by the oscillation frequency and the sampling rate is low

Images