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Preparation method of zero threshold voltage NMOS

A zero-threshold and voltage technology, applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve problems such as zero-threshold voltage NMOS failure

Active Publication Date: 2019-01-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the gate dielectric layer of the zero-threshold voltage NMOS includes ONO and the high-voltage gate oxide dielectric layer. In addition, the ONO dielectric layer will have charge accumulation, resulting in the threshold voltage of the zero-threshold voltage NMOS becoming about 0.8V. Disable zero-threshold voltage NMOS

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  • Preparation method of zero threshold voltage NMOS
  • Preparation method of zero threshold voltage NMOS
  • Preparation method of zero threshold voltage NMOS

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Embodiment Construction

[0017] A preparation method of a zero-threshold voltage NMOS described in the present invention is described as follows in conjunction with a specific embodiment:

[0018] Contains the following steps:

[0019] Step one, such as figure 1 As shown, a layer of thickness is grown on the substrate surface sacrificial oxide layer.

[0020] Step 2: using photoresist to expose the region of the NMOS device, ion implantation to form a P well; under the mask of the photoresist, tunnel doping ion implantation is used for doping to adjust the threshold voltage. Such as figure 2 shown. The threshold voltage of the NMOS injected through the mediation is about -0.8V.

[0021] Step 3, remove the photoresist and sacrificial oxide layer, and then grow a layer of ONO layer on the surface of the substrate, such as image 3 shown.

[0022] Step 4, such as Figure 4 As shown in FIG. 1 , the mask of the P well is used to expose the region of the NMOS device, and the implanted ions of the...

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Abstract

The invention discloses a preparation method of zero threshold voltage NMOS, which comprises the following steps: a sacrificial oxide layer is grown on the surface of a substrate; 2, exposing an areaof the NMOS device, and implanting ions to form a P well; Under the mask of photoresist, doping is carried out by ion implantation process. 3, remove that photoresist and the sacrificial oxide layer,and then grow an ONO layer; 4, exposing the region of the NMOS device by using a mask plate of the P well, and doping the region with an ion implantation process; Removing the ONO layer in the photoresist window; Subsequently remove that photoresist.

Description

technical field [0001] The invention relates to the field of manufacturing technology of semiconductor integrated circuits, in particular to a method for preparing a zero-threshold voltage NMOS. Background technique [0002] As the chip size continues to shrink and functions continue to increase, process costs continue to increase. On the basis of not affecting the performance of the device, saving the photolithography board and reducing the process steps have become the primary considerations for reducing the process cost. The traditional method of preparing memory is to grow a layer of silicon oxide-silicon nitride-silicon oxide (ONO) to prepare a gate dielectric layer through a photolithography plate. In order to reduce the cost, the cost control of the memory preparation is achieved by reducing the ONO photoresist plate in the semiconductor process manufacturing. In this case, the gate dielectric layer of the zero-threshold voltage NMOS includes ONO and the high-voltag...

Claims

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Application Information

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IPC IPC(8): H01L21/336
CPCH01L29/66833
Inventor 单园园胡君陈华伦陈瑜
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP