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Semiconductor structure and its preparation method

A semiconductor and plasma technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as thermal expansion coefficient mismatch, low yield, cumbersome process steps, etc., to reduce coating The effect of the number of craft

Active Publication Date: 2021-01-19
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a semiconductor structure and its method for solving the problem of wafer warpage caused by the mismatch of thermal expansion coefficients in the prior art when forming a large-thickness dielectric layer , products with a large thickness dielectric layer have the problems of low yield, low yield and high cost, and the process steps of forming a large thickness dielectric layer through multiple spin coatings are cumbersome and costly, and the formed dielectric layer is prone to cracking and peeling problems

Method used

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  • Semiconductor structure and its preparation method
  • Semiconductor structure and its preparation method
  • Semiconductor structure and its preparation method

Examples

Experimental program
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Embodiment 1

[0049] see figure 1 , the invention provides a method for preparing a semiconductor structure, the method for preparing a semiconductor structure includes the following steps:

[0050] 1) Provide a base;

[0051] 2) forming a groove with a predetermined depth on the surface of the substrate;

[0052] 3) forming a dielectric layer in the groove, the dielectric layer fills the groove, and the exposed surface of the dielectric layer is flush with the surface of the substrate on which the groove is formed.

[0053] In step 1), see figure 1 Step S1 in and figure 2 , providing a substrate 10 .

[0054] As an example, the substrate 10 may be, but not limited to, a wafer.

[0055] As an example, the wafer may be a bare wafer without any processing, or may be a wafer with power devices (not shown) formed therein. Preferably, in this embodiment, the wafer is a wafer that has completed a previous process.

[0056] In step 2), see figure 1 Step S2 in and image 3 , forming a groov...

Embodiment 2

[0076] read on Figure 8 , the present invention also provides a semiconductor structure, the semiconductor structure comprising:

[0077] A substrate 10, the surface of which is formed with a groove 11 having a predetermined depth;

[0078] A dielectric layer 12 , the dielectric layer 12 is located in the groove 11 , and the exposed surface of the dielectric layer 12 is flush with the surface of the substrate 10 formed with the groove 11 .

[0079] As an example, the substrate 10 may be, but not limited to, a wafer.

[0080] As an example, the wafer may be a bare wafer without any processing, or may be a wafer with power devices (not shown) formed therein. Preferably, in this embodiment, the wafer is a wafer that has completed a previous process.

[0081] As an example, the groove 11 may be formed on the surface of the substrate 10 by using but not limited to a wet etching process.

[0082] As an example, when the substrate 10 is a wafer, since the wafer has completed the...

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Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: 1) providing a substrate; 2) forming a groove with a preset depth on the surface of the substrate; 3) forming a dielectric layer in that groove, wherein the dielectric lay fills the grooves, and the exposed surface of the dielectriclay is flush with the surface of the substrate formed with the grooves. By first forming a groove on the surface of the substrate, Then, a dielectric layer is formed in the groove, and the dielectriclayer located in the groove can indirectly provide a certain thickness of the dielectric layer. When the passive device needs to be fabricated on the substrate surface, the passive device can be directly fabricated on the top of the groove, so that the coating process times of the dielectric layer can be reduced, and problems such as cracking and peeling off of the dielectric layer can be avoidedas much as possible. At the same time, the preparation method of the semiconductor structure of the invention does not occupy the area of the front side of the substrate, does not affect the performance of the front side power device, and is compatible with the integrated circuit back-channel packaging process.

Description

technical field [0001] The invention belongs to the technical field of high-frequency packaging, and in particular relates to a semiconductor structure and a preparation method thereof. Background technique [0002] With the market's urgent need for miniaturization of electronic devices, chip processing and manufacturing technology and chip packaging technology are developing in the direction of high integration, high performance, and low cost. Using wafer-level packaging technology can effectively reduce the package size of the chip, reduce the interconnection distance between the IC and the PCB board, and shorten the production cycle. Rewiring technology is a key technology in wafer-level packaging. It can not only realize the redistribution of pins and increase the interconnection density, but also can be used to integrate passive devices, which is of great significance to the miniaturization of the system. Passive devices are an integral part of electronic systems. Trad...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L23/29
CPCH01L21/02282H01L21/02299H01L21/02315H01L23/29
Inventor 张伟博罗乐徐高卫
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI