Transient voltage inhibition diode and preparation method thereof
A transient voltage suppression, diode technology, applied in the direction of diodes, circuits, electrical components, etc., can solve the problem of high clamping voltage
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Embodiment 1
[0035] In a preferred embodiment, as figure 1 As shown, a transient voltage suppressor diode is proposed, which may include:
[0036] The substrate 10 is P-type, including a front side and a back side respectively defining a central region CE and an edge region EG;
[0037] The protective layer 20 covers the edge region EG of the front surface of the substrate 10 and exposes the surface in the central region CE of the front surface of the substrate 10;
[0038] A first N well W1 is prepared in the central region CE of the front surface of the substrate 10 where the protective layer 20 is exposed, and several gate structures GD are prepared in the first N well;
[0039] The substrate 10 is prepared with a second N-well W2 in the central region CE on the back surface, and an annular P-well W3 surrounding the second N-well W2 in the edge region EG;
[0040] The first metal layer M1 covers the central region CE of the front surface of the substrate 10;
[0041] The second metal...
Embodiment 2
[0050] In a preferred embodiment, as figure 2 As shown, a preparation method of a transient voltage suppression diode is also proposed, and the schematic diagram of the structure formed by each step can be shown as Figure 3-7 Shown, wherein, this preparation method can comprise:
[0051] Step S1, providing a P-type substrate 10, the substrate 10 includes a front side and a back side respectively defining a central region CE and an edge region EG, and a protective layer 20 is covered on the front side edge region EG of the substrate 10 , the protective layer 20 exposes the surface in the central region CE of the front surface of the substrate 10, and a first N well W1 is prepared in the central region CE of the front surface of the substrate 10 exposed by the protective layer 20;
[0052] Step S2, preparing and forming several gate structures GD in the first N well W1;
[0053] Step S3, preparing a first metal layer M1 covering the central region CE of the front surface of ...
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