A boost clock generation circuit

Abstract

The invention discloses a boost clock generation circuit, which is characterized in that the circuit is composed of a charging and discharging unit, a level conversion unit and a digital modulation unit interconnected, wherein the level conversion unit and the digital modulation unit are mainly composed of common MOS tubes connected to each other. The unit works in the high-voltage domain VDDL~VDDH, the low-voltage clock signal is connected to the charging and discharging unit, and is boosted by the level conversion unit and the digital modulation unit, and the output terminals PH1 and PH1B of the digital modulation unit are used as the converted high-voltage clock. signal output. The application of the boost clock generating circuit of the present invention can realize the function of converting the low voltage clock to the high voltage clock, avoid the influence of the use of the high voltage MOS tube and its parasitic capacitance on the switching efficiency, eliminate the extra static current consumption, and optimize the circuit performance. overall energy consumption.

Description

technical field [0001] The invention relates to a signal conversion circuit, in particular to a clock signal generating circuit suitable for converting a common mode power supply of an application system from a low voltage to a high voltage. Background technique [0002] With the rapid development of electronic application technology, as the basis of hardware development, microelectronics is also constantly breaking through and developing in the emerging technical problems. In the microelectronic design of many application systems, although the timing signals used in most circuit designs are low-voltage signals, that is to say, the conventional signal swing is below 5V. However, with the diversification of the functions of the application system, the low-voltage pulse clock signal cannot meet the signal requirements of some high-voltage drives. Therefore, a clock signal generating circuit that increases the voltage needs to be introduced in the circuit design of such functio...

AI Technical Summary

Problems solved by technology

After in-depth analysis and research, the clock generation circuit of this design method also has many defects and deficiencies: firstly, due to the existence of parasitic capacitance of the high-voltage MOS tube itself, the conversion efficiency is greatly limited in the process of charging and discharging, and the overall process sensitivity is strong. , Difficulty; Moreover, the circuit is complex, resulting in the actual power consumption is always maintained at a high level, making it difficult to reduce power consumption

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