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Module and method for correcting sampling time error between time interleaving ADC channels

A technology of time interleaving and sampling time, applied in the direction of analog-to-digital converter, analog/digital conversion, analog/digital conversion calibration/test, etc., to achieve the effect of reducing complexity and hardware consumption, simple algorithm principle, and easy implementation

Active Publication Date: 2019-02-19
SOUTHEAST UNIV
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Problems solved by technology

For Nyquist-type ADCs, it is one of the current research hotspots to design a correction method with as weak a constraint on the input analog signal as possible, but there is no ideal correction method yet.

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  • Module and method for correcting sampling time error between time interleaving ADC channels
  • Module and method for correcting sampling time error between time interleaving ADC channels
  • Module and method for correcting sampling time error between time interleaving ADC channels

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Embodiment Construction

[0047] The technical solutions provided by the present invention will be described in detail below in conjunction with specific examples. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0048] figure 1 It is a time-interleaved ADC that includes a correction module for sampling time errors between time-interleaved ADC channels; where the time-interleaved ADC consists of a multi-channel clock generation module (Multi-phase clock generator), an analog-to-digital conversion module (ADC), and an error correction module, data composite module (MUX), and the error correction module includes: reference channel unit, error detection unit (Digital detection) and delay line unit (Delayline);

[0049] Wherein, the input end of the multi-channel clock generation module is connected to an external clock signal source, the first output end to the Mth output en...

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Abstract

The invention provides a module for correcting sampling time error between time interleaving ADC channels, which comprises a reference channel unit, an error detecting unit and a delay line unit. A corresponding correction method is provided, and the correction method is executed in parallel between M single channels of the error detecting unit. According to the correction module and the correction method in the invention, the detection and calibration of the sampling time error of a time interleaving ADC of any channel number can be completed with moderate hardware cost and low hardware complexity; the calibration precision is high; and higher calibration precision and shorter correction time can be achieved for a high frequency analog signal. The algorithm principle of the correction method is simple and easy to implement, thereby reducing the complexity and hardware consumption of the circuit design.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, and relates to a correction module and a correction method for sampling time errors between time-interleaved ADC channels. Background technique [0002] An analog-to-digital converter (ADC for short) is an electronic device that converts an analog signal into a digital signal. The working process of the ADC can be roughly divided into four steps: sampling, holding, quantization and encoding. The two core indicators of the ADC are conversion rate (that is, sampling rate) and conversion accuracy. Conversion accuracy is characterized by resolution and conversion error. The resolution is expressed by the number of digits of the ADC output digital signal, and the unit is bit (bit). The conversion error refers to the difference between the ideal value and the actual value of the output digital code of the ADC. Usually differential nonlinearity (DNL) and integral nonlinearity (IN...

Claims

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Application Information

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IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/1004H03M1/1057H03M1/1215
Inventor 曹宇苗澎黎飞王欢
Owner SOUTHEAST UNIV
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