A memory cell and a static random access memory

Abstract

Embodiments of the present invention relate to a memory cell and a static random access memory. The memory cell includes a latch that provides a first memory bit. The memory cell further includes a first MOS transistor. The gate electrode of the first MOS transistor is connected with the first memory bit, the source electrode of the first MOS transistor is connected with a first read line, and thedrain electrode of the first MOS transistor is connected with a second read line. In a first state, the first read line is a read word line and the second read line is a read bit line. In a second state, the second read line is a read word line and the first read line is a read bit line. The memory cell of the embodiment of the invention can realize the interchange of the read word line and the read bit line.

Description

technical field [0001] The invention relates to the storage field, in particular to a storage unit and a static random access memory (Static Random Access Memory, SRAM). Background technique [0002] figure 1 It is a schematic diagram of a memory cell structure of a traditional SRAM. The storage unit adopts an ordinary six-tube unit, which is composed of six metal-oxide-semiconductor (MOS) field effect transistors, and the MOS field effect transistors are referred to as MOS transistors for short. refer to figure 1 , the memory cell includes two inverting gates and two MOS transistors. Among them, the two inverting gates are composed of four MOS tubes, the two inverting gates in the figure form a latch for storing data, and the two MOS tubes in the figure are used for gating access. A latch connected circularly by two inverting gates exists in two stable states, 0 and 1. Wherein, A and B are two storage bits with opposite states. For example, when storage bit A is logic ...

AI Technical Summary

Problems solved by technology

When reading data for traditional SRAM, usually only the data of a certain address can be read. If you want to obtain the data of this address about the diagonal symmetric address of the matrix, you need to write the algorithm in the code of the peripheral digital circuit of the SRAM. to process, which is slow and has high power consumption and workload

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