Memory cell, device, memory cell array and method of operation

Abstract

This application disclosed a storage unit, device, storage unit array and its operation methods, involving the field of memory technology.The storage unit includes: the second secondary pipe, the bottom electrode, the top electrode, and the data storage material layer between the bottom electrode and the top electrode and the top electrode.The first two pole tube includes: the first trap area in the substrate; the first N -type doped area is adjacent to the first trap area and connected to the position line; and the first P type doped areaThe area is adjacent and is separated from the first N -type doped interval.The second and second poles include: the second trap area in the substrate, the same type of conductivity in the first trap area; the second N -type doped area, adjacent to the second trap area; and the second P type doped areaIt is adjacent to the second trap area and connected to the reset line, and is separated from the second N -type doped interval.The bottom electrode is connected to the first P type doped area and the second N -type doped area, respectively.The top electrode is connected to the word line.This application can increase the position and reset current.

Description

technical field [0001] The present application relates to the technical field of memory, and in particular to a storage unit, a device, a storage unit array and an operation method thereof. Background technique [0002] For resistive memory (RRAM) or phase change memory (PCRAM), the array architecture of 1T1R (one transistor and one resistive or phase change memory) is a common array architecture. Compared with the 1T1R array architecture, the 2D1R (2 diodes and 1 resistive change or phase change memory) array architecture can obtain higher operating current, lower leakage current and higher array density. [0003] In an existing 2D1R array architecture, the first diode of the two diodes includes a P+ doped region and an N well, that is, a PN junction is formed at the interface of the P+ doped region and the N well; The second diode includes an N+ doped region and a P well, that is, a PN junction is formed at the interface of the N+ doped region and the P well. In such a 2...

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Problems solved by technology

[0004] However, the inventors of the present application found that: the set current (set current) and the reset current (reset current) of the above-mentioned 2D1R array architecture are relatively small

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