A chip security monitoring method and a security monitoring chip

A security monitoring and chip technology, applied in computer security devices, instruments, platform integrity maintenance, etc., can solve the problems of increasing the complexity of chip design and the integrity of verification cannot be guaranteed, and achieve security guarantees and avoid performance problems. The loss, the effect of large inclusion

Active Publication Date: 2019-03-22
成都奥卡思微电科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Chip security risks can be discovered and eliminated by using targeted verification methods in the design process, but there are two major disadvantages in doing so: first, the complexity of chip design is increasing, and the integrity of verification cannot be guaranteed; second, many chip security The vulnerability itself is the result of chip performance optimization, such as the aforementioned branch prediction and out-of-order execution

Method used

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  • A chip security monitoring method and a security monitoring chip
  • A chip security monitoring method and a security monitoring chip
  • A chip security monitoring method and a security monitoring chip

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0048] Embodiment 1 provides a chip security monitoring method. This embodiment includes the monitoring of known attack modes, and also covers unknown attack modes that can be ruled out. Specifically, this method includes the following steps:

[0049] A monitor embedded in the chip monitors the operation of the chip;

[0050] Wherein, the monitor includes a first state machine and / or a second state machine, the first state machine is corresponding to a model established by a known chip attack, and the second state machine is obtained by The security rules / security properties described by the assertion are transformed.

[0051] Wherein, in this embodiment, the function of the monitor is to give an alarm or interrupt the operation of the chip when the chip is attacked, so as to prevent confidential information from being leaked or tampered with.

[0052] The state machine model of the monitor is built into the chip as part of the chip design and tapeout.

[0053] There are tw...

Embodiment 2

[0087] This embodiment provides a security monitoring chip. This embodiment has the same inventive concept as Embodiment 1, specifically, as image 3 As shown, the chips include:

[0088] chip body;

[0089] and a monitor embedded in the chip body, the monitor monitors the operation of the chip body;

[0090] Wherein, the monitor includes a first state machine and / or a second state machine, the first state machine is corresponding to a model established by a known chip attack, and the second state machine is obtained by The security rules / security properties described by the assertion are transformed.

[0091] Among them, such as image 3 As shown, the number of monitors is n.

[0092] More preferably, in this embodiment, the monitor includes an initial state and at least one tracking state, and the tracking state includes at least one error reporting state;

[0093] The monitoring of the operation of the chip body includes:

[0094] The monitor makes a judgment on the s...

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Abstract

The invention discloses a chip safety monitoring method and a safety monitoring chip. The method comprises the following steps: a monitor embedded in the chip monitors the chip operation; Wherein themonitor comprises a first state machine corresponding to a model established by a known chip attack and / or a second state machine converted from a security rule / security attribute described by an assertion. The monitor of the invention covers both known attack modes and unknown attack modes that can be excluded by security attributes. Especially the monitor based on security attributes, because ofthe expressive power of assertion language, the security attributes will be very inclusive, and the chip design does not need complex and time-consuming security attributes verification, and also avoids the possible performance loss caused by filling security loopholes.

Description

technical field [0001] The invention relates to the field of chip security, in particular to a chip security monitoring method and a security monitoring chip. Background technique [0002] Chip security has attracted widespread attention in the information industry recently. The Specter and Meltdown exploits, which were discovered in early 2018, exploit the branch prediction and out-of-order execution commonly used in chip design to perform high-speed reading of highly confidential memory information, seriously threatening a variety of processors from Intel, AMD, and ARM. [0003] Chip security risks can be discovered and eliminated by using targeted verification methods in the design process, but there are two major disadvantages in doing so: first, the complexity of chip design is increasing, and the integrity of verification cannot be guaranteed; second, many chip security The vulnerability itself is the result of chip performance optimization, such as the aforementioned...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/55G06F21/57G06F21/71
CPCG06F21/552G06F21/577G06F21/71
Inventor 袁军曹皖林
Owner 成都奥卡思微电科技有限公司
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