A semiconductor structure and a manufacturing method thereof

Abstract

A semiconductor structure and a manufacturing method thereof are disclosed. An asymmetric CPP layout for a semiconductor structure with a different gate pitch is provided to mitigate gate-to-gate parasitic capacitances, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductorstructure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof. Background technique [0002] Fin field effect transistors (finFETs) have several advantages over planar field effect transistors, such as (i) reduced power consumption, (ii) improved threshold voltage control, (iii) channel control, and (iv) leakage current characteristics. However, due to the surface area between the fin and the gate, the parasitic capacitance (such as between the source / drain (S / D) contact and the gate structure) of the FinFET compared to the planar MOSFET May be larger. The parasitic capacitance will affect the cut-off frequency of the field effect transistor (f T ) have an adverse effect, while the cutoff frequency sets a boundary for the frequency response of the field effect transistor. Contents of the invention [0003] According to various embodiments of the present disclosure, a semiconductor structure is provided...

AI Technical Summary

Problems solved by technology

However, due to the surface area between the fin and the gate, the parasitic capacitance (such as between the source / drain (S / D) contact and the gate structure) of the FinFET compared to the planar MOSFET may be larger

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