Mapping method based on general reconfigurable processor dbss and mbss

Abstract

The invention provides a mapping method based on the universal reconfigurable processors DBSS and an MBSS. The method comprises the steps of carrying out the segmentation of a loop into a loop controlbasic block and a loop body basic block, enabling the loop control basic block to comprise a basic operator, and enabling the loop body basic block to comprise a loop body; constructing a first directed graph description data dependency relationship according to the basic operator of the basic block of the loop body; constructing a data flow graph according to the basic operator of the cyclic control basic block, and constructing a second directed graph to describe the control dependency relationship between the basic blocks according to the control dependency relationship of quality inspection of the cyclic control basic block and the cyclic body basic block; combining the cyclic control basic block and the cyclic body basic block into a mixed data control flow graph; and mapping the mixed data control flow graph. The method has great advantages in speed, performance and power consumption in the application of processing uncertain loop boundaries.

Description

technical field [0001] The present invention relates to the field of data processing, in particular to a mapping method based on a general reconfigurable processor DBSS (Dynamic Boundary, Static Schedule) and MBSS (Mixed Boundary, Static Schedule). Background technique [0002] Currently, spatial programming structures (such as FPGA and CGRA, Coarse-grained Reconfigurable Architectures) have been widely used in computing-intensive applications. The FPGA has a high degree of parallelism, but it is limited to fine-grained calculations. CGRA, as a coarse-grained mixed processor architecture, can reduce power consumption and improve performance while providing parallelism. However, the performance of CGRA relies heavily on compiler technology, and it is still a huge challenge to provide efficient algorithm mapping for complex applications. [0003] Generally speaking, a general-purpose reconfigurable processor includes four parts. The first is the PEA array (processing element...

AI Technical Summary

Problems solved by technology

For application scenarios where the loop boundary is not fixed, the existing technology uses the maximum loop boundary for loop unrolling. This technique will cause some invalid instructions to be issued, which not only has the problem of low speed and efficiency bottleneck, but also brings additional power consumption

In addition, DISE and state-based full prediction techniques can handle CFG mapping, but DISE and state-based full prediction mainly deal with branch (if-else) structures, and can only deal with the innermost loop body part

For DFG and CFG with uncertain loop boundaries, and nested loops, there is no existing technology to solve

Images