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A wide XOR circuit optimization method

An optimization method and circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., to achieve the effect of reducing the running time, area and delay of logic synthesis

Active Publication Date: 2019-04-26
XIAN INTELLIGENCE SILICON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When n is relatively large, the minimum number of items in the coverage table will grow exponentially and become very large, which will bring great challenges to the running time and storage space of the logic synthesis system

Method used

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  • A wide XOR circuit optimization method
  • A wide XOR circuit optimization method
  • A wide XOR circuit optimization method

Examples

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Embodiment 1

[0044] figure 1 A flow chart of a broadband or circuit optimization method provided by an embodiment of the present invention, including:

[0045] Find the root XNOR according to the netlist of the circuit to be optimized;

[0046] forming an XNOR cone from said root XNOR;

[0047] Carry out common end extraction to described XNOR cone;

[0048] Decompose the XNOR cone according to the preset rules, and store the decomposition results in the netlist.

[0049] In the logic synthesis system, XNOR optimization is specially treated separately, and the general combinational logic optimization (two-level logic optimization and multi-level logic optimization) for general combinational logic, such as AND gate and OR gate, is not processed.

[0050] XNOR optimization is divided into two parts in the process, which run at the beginning and end of combinatorial logic optimization respectively. At the beginning of logic optimization, related XNOR gates are grouped, and the grouped res...

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Abstract

The invention discloses a wide XNOR circuit optimization method. The method comprises the following steps: searching a root XNOR according to a to-be-optimized circuit netlist; Forming an XNOR cone according to the root XNOR; Carrying out common end extraction on the XNOR cone; And decomposing the XNOR cone according to a preset rule, and storing a decomposition result in a netlist. According to the wide XOR circuit optimization method provided by the invention, optimization operations such as grouping decomposition and common end extraction are carried out on the circuit netlist to be optimized, so that the overall logic comprehensive operation time is remarkably reduced, and the area and delay of a generation circuit are reduced.

Description

technical field [0001] The invention belongs to logic circuit optimization, and in particular relates to a method for widening or circuit optimization. Background technique [0002] Logic synthesis, in the EDA (Electronic Design Automation) tool, is to perform logic optimization and process mapping on the logic-level description of digital circuits, and generate process-related components that meet user constraints (such as area, timing, power consumption, etc.) Gate-level process netlist. Logic optimization includes combinational logic optimization and sequential logic optimization, and combinational logic optimization is to optimize combinational logic circuits, including two-level logic optimization and multi-level logic optimization. In logic synthesis based on overlay table representation, an n-input XNOR (exclusive OR) gate will have 2 n-1 minimum item. When n is relatively large, the minimum number of items in the coverage table will grow exponentially and become v...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/327Y02D10/00
Inventor 王作建朱明贾红陈维新韦嶔程显志
Owner XIAN INTELLIGENCE SILICON TECH INC
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