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An efficient multifunctional verification platform and method

A verification platform and verification method technology, applied in the field of efficient multi-functional verification platform, can solve the problems of poor object-oriented support, complex construction and maintenance, complex design circuit, etc., to facilitate viewing, shorten verification cycle, and simplify construction and maintenance. Effect

Active Publication Date: 2019-05-07
HUNAN ADVANCECHIP ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the verification methodology, VMM (Verification Methodology Manual) was developed earlier and has more mature verification components, but its object-oriented support is poor, and each class is complicated to use; OVM (Open Verification Methodology) was proposed later , the open source is good, the number of classes is large, but the use is more complicated; UVM (Universal Verification Methodology) combines the methods of VMM and OVM, but its components are many, and the construction and maintenance are more complicated
[0004] With the increasing scale of integrated circuits and the increasing complexity of designed circuits, there is an urgent need for an efficient multi-functional verification platform and method to solve the problems existing in the prior art

Method used

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  • An efficient multifunctional verification platform and method
  • An efficient multifunctional verification platform and method
  • An efficient multifunctional verification platform and method

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Experimental program
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Embodiment 1

[0044]A verification platform is the layer of code established to apply input stimuli to the design object under test. This piece of code is used to generate a predetermined sequence of inputs for a design and then selectively observe the responses. The verification platform is a closed system, which is formed by inputting stimulus to the design to be verified and observing the output response of the design to be verified. Specifically as figure 1 As shown, a multifunctional verification platform provided by this embodiment includes the following modules:

[0045] Test platform TB, including the test platform top-level file and the macro definitions required by the test platform. The top-level file of the test platform contains the connection method between the design to be verified and the test case, the conditions for simulation running after calling, and the format of the saved waveform; the macro definition is used to simplify the test case to monitor the internal signal...

Embodiment 2

[0054] like figure 2 The shown flow chart of the multi-function verification method, the multi-function verification method described in the second embodiment of the present invention, is performed using the multi-function verification platform described in claim 1, and includes the following steps:

[0055] Step S100, read the configuration file of the verification platform execution module, where the configuration file includes the variables required by the platform, the paths of each file, and the keywords in the marked verification report. After starting the execution file, enter the required instructions, first obtain the verification platform configuration file, assign values ​​to the variables required by the platform according to the content in the verification platform configuration file, and mark the keywords in the verification report, etc.

[0056] Step S102, parse the command input by the terminal, the command includes case number, module name, macro definition r...

Embodiment 3

[0065] When verifying a single case, after starting the execution file run.sh file in the execution module, enter the required commands. The multifunctional verification platform is as follows: Figure 4 The flow of steps shown is carried out.

[0066] Step S200, read the verification platform configuration file, the configuration file includes the variables required by the platform, the paths of each file, and the keywords in the marking verification report. According to the content in the verification platform configuration file, assign values ​​to the variables required by the platform, mark keywords in the verification report, etc.

[0067] Step S202, parse the command input by the terminal, the command includes case number, module name, macro definition required for verification, coverage command, recompile command, record waveform command, timing check command, post-simulation command, and save memory data command , random number directives, and pragma directives.

[...

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Abstract

The invention discloses an efficient multifunctional verification platform and method, and the platform comprises: a test platform TB which comprises a test platform top file and a macro definition required by the test platform; The memory module MEMORY which comprises data required to be initialized by a memory; The netlist module NETLIST which comprises a rear imitation netlist and a delay file;The RTL module RTL which comprises a model required by the design and test platform to be verified; The execution module RUN which comprises a configuration file and an execution file of the test platform, wherein the execution file comprises a run.sh file and a cov.sh file; And the test case module TC which comprises a test case and a common function. According to the multifunctional verification platform and method disclosed by the invention, one case can be verified independently, and a plurality of cases can be verified in parallel; Verification results are mutually independent and are saved in respective spaces, data interaction between the CPU and the verification environment is simple and clear during system-level verification, the verification efficiency is improved, and in addition, establishment and maintenance of the verification platform are relatively simple.

Description

technical field [0001] The invention relates to the field of digital integrated circuit design, in particular to an efficient multifunctional verification platform and method. Background technique [0002] With the continuous improvement of the chip manufacturing process and the continuous improvement of the integration degree, integrated circuits have experienced the development stages of small-scale integration, medium-scale integration, large-scale integration, ultra-large-scale integration, and now very large-scale integration. With the continuous increase of circuit scale and the increasing number of design functions, verification work faces new challenges. Moore's Law states that the number of transistors that an integrated chip can accommodate doubles every about 18 months, and its performance also doubles. This makes the complexity of the chip higher and higher, and the verification work has become a key bottleneck in the chip design, usually accounting for more tha...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCY02D10/00
Inventor 刘洋黄嵩人陈毅华张巍
Owner HUNAN ADVANCECHIP ELECTRONICS TECH CO LTD