FPGA verification method of jesd204b controller

Abstract

The invention relates to a JESD204B controller verification method, comprising the steps of: (1-1), establishing a transmission verification link from a transmitting end of a JESD204B controller to be verified to a benchmark receiving module; (1-2), establishing a slave benchmark transmitting module Receive verification link to the receiving end of the JESD204B controller to be verified; (1‑3), perform link layer verification to verify whether the link code group synchronization and initialization channel alignment functions of the JESD204B controller to be verified are correct; (1‑4) , Carry out transport layer verification, verify whether the JESD204B controller link configuration data to be verified is consistent with the JESD204B protocol, and whether the mapping function of sampling data and frame data is correct; (2-1) After the logic function simulation verification is passed, the to-be-verified The JESD204B controller transmitter and receiver codes are downloaded to the FPGA corresponding to the transmission verification system to complete the board-level test verification. The invention combines simulation and upper-board debugging to simulate the application conditions of the JESD204B controller, thereby improving the completeness and accuracy of the JESD204B controller verification.

Description

technical field [0001] The invention relates to an FPGA verification method and process for RTL-level source codes of digital integrated circuits, in particular to a FPGA verification method of a JESD204B controller, and belongs to the technical field of digital integrated circuit prototype verification and simulation. Background technique [0002] JESD204B is mainly used for high-speed data transmission protocol between ADC or DAC and FPGA. It can convert parallel data into high-speed serial data or convert high-speed serial data into parallel data. [0003] In April 2006, the initial version of JESD204B, JESD204, was released, which described a multi-gigabit serial data link between a converter and a receiver (typically an FPGA or ASIC). [0004] JESD204A was published in April 2008. The ability to support multiple aligned serial channels under multiple converters has been added in this release. The supported channel data rates for this release are 312.5Mbps to 3.125Gbp...

AI Technical Summary

Problems solved by technology

[0006] The JESD204B protocol has a transport layer, a link layer, an application layer, and a physical layer. The physical layer is a high-speed serial-to-parallel converter, which involves a digital-analog hybrid circuit. Its performance is closely related to the process and layout. Generally, tools are used for simulation verification. Board-Level Verification Using FPGAs

[0007] Existing JESD204B controllers have few verification technologies. Generally, software model function simulation is performed according to verification requirements. There is no dedicated hardware verification system and verification method that meets the protocol requirements.

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