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VDMOS device modeling method and VDMOS device modeling model

A technology of device and model parameters, which is applied in the fields of instruments, calculations, electrical digital data processing, etc., to achieve the effect of improving the modeling accuracy

Pending Publication Date: 2019-05-28
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a VDMOS device modeling method and model, which solves the problem of lacking a standard SPICE model to accurately describe the characteristics of JFET resistance and drift region resistance in power VDMOS devices

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  • VDMOS device modeling method and VDMOS device modeling model
  • VDMOS device modeling method and VDMOS device modeling model
  • VDMOS device modeling method and VDMOS device modeling model

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Embodiment Construction

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0028] It should be noted that like numerals and let...

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Abstract

The embodiment of the invention provides a VDMOS device modeling method and a VDMOS device modeling model. The VDMOS device modeling method comprises the steps of establishing a sub-circuit model corresponding to a VDMOS device comprising a drain end parasitic resistor; introducing a first-order fitting coefficient, a second-order fitting coefficient and a coupling coefficient to define the valueof the drain end parasitic resistor, and obtaining a definition function of the value of the drain end parasitic resistor; and obtaining model parameters including the first-order fitting coefficient,the second-order fitting coefficient and the coupling coefficient according to the test data of the VDMOS device sample and the definition function. The method and the model solve the problem that atpresent, a standard SPICE model is lacked to accurately describe JFET resistance and drift region resistance characteristics in the power VDMOS device.

Description

technical field [0001] The invention relates to the technical field of semiconductor device design simulation, in particular to a VDMOS device modeling method and model. Background technique [0002] Power device (VDMOS) combines power electronics technology and microelectronics technology. Its development is based on MOS integrated circuit technology. It is a key and basic product for the transformation of power electronics from low frequency to high frequency and the breakthrough of power frequency conversion. [0003] It can be seen from the working principle of VDMOS devices that VDMOS devices have many characteristics different from ordinary MOSFETs. Because it is a vertical conductive structure, there is a parasitic junction field effect JFET between the P wells; due to the need to ensure a high breakdown voltage, it is necessary to A drift region that withstands high voltage breakdown has a parasitic diode and drift region resistance. At the same time, its internal ca...

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Application Information

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IPC IPC(8): G06F17/50
CPCY02D10/00
Inventor 卜建辉宋李梅王成成罗家俊韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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