A high-speed sense amplifier circuit of an SRAM type memory

A technology of sense amplifier and memory, applied in static memory, digital memory information, information storage and other directions, can solve the problems of large input voltage difference and affect the reading speed of memory, reduce the requirement of input voltage difference and improve the response speed and processing power, the effect of speeding up the reading of "0"
CN109841240AActive Publication Date: 2019-06-04BEIJING MXTRONICS CORP +1
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
BEIJING MXTRONICS CORP
Publication Date
2019-06-04

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Abstract

The invention relates to a high-speed sensitive amplifier circuit of an SRAM (Static Random Access Memory) type memory, which accelerates the overall response speed of a latch amplifier through positive feedback by virtue of the charge retention characteristic of a capacitor C1 when reading a '1' memory cell, so that the requirement of the amplifier on the input voltage difference is greatly reduced, and the speed of the SRAM type memory for reading the '1' is accelerated; When the '0' storage unit is read, the storage data is read by virtue of the fast pull-up action of the transistor MP5 through the control on the NAND gate I1 by the hopping of the read enable signal S, so that the requirement on the input voltage difference is greatly reduced, the reading speed of the sense amplifier isaccelerated, and the speed of the SRAM for reading the '0' is accelerated. The requirement of the sensitive amplifier for the input voltage difference is reduced, and the reaction speed and the processing capacity of the sensitive amplifier are improved.
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Description

technical field

[0001] The invention relates to a high-speed sensitive amplifier circuit of an SRAM memory, which belongs to the field of memory circuit design. Background technique

[0002] Read and write speed is a key indicator to measure the performance of SRAM type memory. Since the read operation of SRAM type storage generally takes longer than the write operation, the read speed becomes the key. The read operation time refers to the time required from address signal input to data output, which is mainly determined by the delay of address signal input IO, row and column decoder, storage unit, sense amplifier and output IO unit. To reduce the reading time, there are usually two options: one is to shorten the time-consuming from the input of the address signal to the opening of the word line, but because the structure of the row-column decoder and other circuits is basically fixed, it is necessary to improve these circuits. The effect of reducing the delay is not obvio...

Claims

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