Memory erasing method and device

A memory and over-erase technology, applied in static memory, read-only memory, information storage, etc., can solve problems affecting normal use, leakage of memory storage cells, etc., to reduce the time required, increase the threshold voltage, and narrow the range of values. Effect

Pending Publication Date: 2019-06-11
GIGADEVICE SEMICON (BEIJING) INC
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0004] The present invention provides a memory erasing method and device to solve the problem that the abnormal power-off of the existing memory causes the serious leakage of the memory unit and affects the normal use of the problem

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Embodiment Construction

[0018] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

[0019] In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe various operations (or steps) as sequential processing, many of the operations may be performed in parallel, concurrently, or simultaneou...

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Abstract

The embodiment of the invention discloses a memory erasing method and device. The memory erasing method comprises the following steps: detecting a power-on signal of a memory; and controlling a plurality of memory blocks in the memory to carry out over-erase verification operation at the same time, so that the threshold voltages of all memory units in the memory are greater than zero voltage. According to the technical scheme provided by the embodiment of the invention, the problems of serious electric leakage of the storage unit and influence on normal use caused by abnormal power failure ofthe existing memory can be solved.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor storage, and in particular, to a memory erasing method and device. Background technique [0002] There are often two types of operations for storage cells in non-volatile memories (such as NOR-FALSH), programming and erasing. The existing erasing operation specifically includes: performing an erasing operation on the storage unit, modifying the data "0" in the storage unit to data "1"; performing an erasure verification operation, and changing the data in the erased storage unit to "1". The threshold voltage of the over-erased (threshold voltage less than zero) memory cell is raised to greater than zero; erase verification is performed to detect whether there are unerased memory cells, and if so, the erase operation is performed again. [0003] However, in a system using non-volatile memory, the power supply may be abnormally powered off due to special reasons. Before...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/14G11C16/04G11C16/34
Inventor 张建军马向超
Owner GIGADEVICE SEMICON (BEIJING) INC
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