Three-dimensional system chip test resource optimization method and system

A system chip and test resource technology, applied in the field of 3D system chip test resource optimization, can solve problems such as not considering test scheduling problems, small test time, etc.

Active Publication Date: 2019-06-18
HARBIN NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the research on 3D system chip test optimization mainly focuses on obtaining the optimal test time or test scheduling. For example, Pradhan analyzed how the stacking order of wafers affects the test time of the entire stacked 3D system chip, and proposed the optimal stacking order. Obtained Algorithms for minimum test time; LAnderegg, S Eidenbenz et al. proposed a 3D SoC die-level test enclosure and test structure suitable for pre-bond testing and post-bonding testing. This method is very practical, but it does not consider the test scheduling problem

Method used

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  • Three-dimensional system chip test resource optimization method and system

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Embodiment 1

[0063] like figure 1 As shown, a method for optimizing 3D SoC test resources is used to optimize 3D SoC test resources and / or test scheduling, including Step 10: Establishing an STO model based on Stackelberg game theory; Step 11: Establishing a game model; Step 12: Initializing Test strategy; Step 13: Find the optimal test strategy.

[0064] like figure 2 As shown, the STO model established in step 10 includes M resource managers (ResourceManager, RM) and N consumers (Consumer Unit, CU), and the resource manager RM manages test resources, and the Consumers consume test resources, the test resources include the number of available TSVs, test time, test bandwidth, that is, at least two of the number of I / O pins in each layer of the 3D system chip, and the record set L={1,2,... , M}, set V={1,2,...,N}. In the STO model, the optimal test bandwidth allocation is provided for the CU, and all the demands of the CU are provided by the RM. Finally, an equilibrium state is formed ...

Embodiment 2

[0079] A three-dimensional system chip test resource optimization system, including a processor and a storage medium, the storage medium stores a program, the program is designed according to the method for optimizing three-dimensional system chip test resources, and the program is executed when the processor runs Method steps:

[0080] Step 10: Establish an STO model based on Stackelberg game theory;

[0081] Step 11: Establish a game model;

[0082] Step 12: Initialize the test strategy;

[0083] Step 13: Find the optimal testing strategy.

[0084] The program is also used for inputting three-dimensional SoC testing constraints, the testing constraints include at least one of the number of available TSVs and the number of test pins. The program is also used to output an optimal test strategy, and the optimal test strategy includes at least one of a test scheduling strategy and a wafer bandwidth allocation strategy.

Embodiment 3

[0086] In order to verify the technical effect of the present invention, the 3D SoC is tested according to the optimal test strategy formed by the present invention, and the test results are compared with the test results of the most mature greedy algorithm and the method proposed by Testrail.

[0087] Firstly, three 3D SoCs are built from d695, f2126, p22810, p34292 and p93791 in ITC'02 (test reference circuit), and they are named 3D SoC1, 3D SoC2 and 3D SoC3 respectively. The specific structure of 3D SoC1 is The reference circuits p93791, p34292, p22810, f2126, and d695 are arranged from top to bottom, and the complexity of the reference circuits is higher as you go upward; the specific structure of 3D SoC2 is to arrange the reference circuits d695, f2126, p22810, p34292, p93791, the lower the reference circuit is, the more complex it is; the specific structure of 3D SoC3 is to arrange reference circuits f2126, p22810, p93791, p34932, and d695 from top to bottom, and the refe...

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Abstract

The invention provides a three-dimensional system chip test resource optimization method and system. The method comprises steps that an STO model is built based on the Stackelberg game theory; a gamemodel is built; test strategies are initialized; the optimal test strategy is searched, the system is designed based on the method, and steps of the method are performed. The method is advantaged in that the brand new design thinking is employed, under the test constraints, the optimal test strategy is searched through the Stackelberg game theory, test resources are optimized, and the optimal testtime and the test bandwidth are obtained.

Description

technical field [0001] The present invention relates to the field of chip testing, in particular to a 3D system on chip (3D System on Chip, 3DSOC) testing resource optimization method and system. Background technique [0002] The rapid development of semiconductor industry manufacturing technology has laid a solid foundation for more complex high-speed chip manufacturing. The three-dimensional system chip manufacturing centered on vertical silicon vias (TSV) is a very promising chip manufacturing technology. It has obvious advantages in increasing the interconnection density, reducing the length of the interconnection line, reducing the size of the package, and reducing power consumption. Vertical through-silicon via (TSV) is an interconnection via vertically passing through a silicon substrate filled with conductive materials, which shortens the length of interconnection lines between wafers on two three-dimensional chips, and is mostly used for functional interconnection. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G06Q10/04
Inventor 邵晶波赵月黄玉妍丁金凤李英梅赵微肖鑫张伟刘晓晓
Owner HARBIN NORMAL UNIVERSITY
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