Check patentability & draft patents in minutes with Patsnap Eureka AI!

IDF lead frame-based semiconductor product package method

A lead frame and packaging method technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions, can solve problems such as poor compatibility, complex mold design, etc., to reduce precision requirements, wide adaptability, Increase the effect of the process flow

Active Publication Date: 2019-06-18
SHENZHEN STS MICROELECTRONICS
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a packaging method based on an improved IDF lead frame, which can solve the problems of complex mold design and poor compatibility of traditional lead frames during molding.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • IDF lead frame-based semiconductor product package method
  • IDF lead frame-based semiconductor product package method
  • IDF lead frame-based semiconductor product package method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] The present invention is improved on the basis of the traditional IDF lead frame, that is to say: the IDF lead frame of the improved semiconductor product includes N columns of chip groups, N≥1, between two adjacent columns of chip groups through the first The connecting ribs are connected; each chip group includes two chip units, each chip unit includes a patch area and a pin area, and the pins in the pin areas of the two chip units of each column are staggered and arranged in phase. Adjacent pins are connected through corresponding second connecting ribs. A concealed pin with a preset width is set between adjacent pins of each chip unit, the first end of the concealed pin is fixed on the second connecting rib, and the second end of the concealed pin extends toward the patch area of ​​the chip unit And keep a preset gap with the edge of the patch area.

[0035] Among them, the hidden pin is a specific pin structure provided by the technical solution of the embodiment ...

Embodiment 2

[0044] Based on the improved IDF lead frame of semiconductor products provided by the present invention, the present invention also proposes a corresponding packaging method, the packaging method including a patch step, a wire bonding step, a molding step, an electroplating step and a rib cutting step. Such as image 3 and 4 As shown, among them, image 3 Represents a schematic flow chart of the packaging method of a traditional IDF lead frame, Figure 4 It is a schematic flow chart showing the packaging method of the IDF lead frame provided by the present invention. From image 3 and Figure 4 It can be seen that due to the improvement of the lead frame, the molding step and rib cutting step in the packaging method are obviously different. The specific packaging method is as follows:

[0045] Mounting step: paste the chip on the mounting area of ​​the lead frame, so that the chip is fixed in the mounting area. Since there is not only one chip unit on the lead frame, mul...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an IDF lead frame-based semiconductor product package method. The IDF lead frame comprise N lines of chip groups, wherein N is more than or equal to 1, two adjacent lines of chip groups are connected by first connection ribs, each line of chip group comprises two chip units, each chip unit comprises a patch region and a pin region, pins of the pin regions of the two chip units are arranged in a staggered way, adjacent pins are connected by a corresponding second connection rib, an invisible pin with a preset width is arranged between adjacent pins of each chip unit, a first end of the invisible pin is fixedly arranged on the second connection rib, a second end of the invisible pin extends to the patch region of the chip unit, and a preset gap is reserved between thesecond end of the invisible pin and an edge of the patch region. The invisible pin and the connection ribs of the lead frame are removed in a package rib cutting process, the problem that a die sealing material cannot be filled between adjacent pins and the patch region of the chip unit during die sealing is solved, and the design accuracy of a package die is also greatly reduced.

Description

technical field [0001] The present invention relates to a lead frame of a semiconductor product, in particular to a packaging method of a semiconductor product based on an IDF (full name: Inter-Digitated leadframe, interdigitated lead frame) lead frame. Background technique [0002] The IDF lead frame provided by the prior art improves the production efficiency of pin-separated device products by rationally designing the staggered arrangement of chip patch areas and pin areas. However, due to the relatively large gaps between the staggered pins, when the prior art pin separation device products are packaged, bosses need to be provided on the mold so that the bosses are embedded in the ribs and patch areas of the lead frame. The empty space between the pins in the area between to prevent the resin from being filled into the empty space when filling. However, due to the different sizes of the pins of lead frames of different specifications, the size of the blank space between...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/56H01L23/495
CPCH01L2224/48091H01L2224/49113H01L2924/00014
Inventor 王勇周杰余蓥军杨晓东都俊兴
Owner SHENZHEN STS MICROELECTRONICS
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More